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* x86: apl: Reduce size for TPLSimon Glass2021-01-051-1/+1
| | | | | | | | | | Update various drivers to use of_match_ptr() and to avoid including debug strings in TPL. Omit the WiFi driver entirely, since it is not used in TPL. This reduces the TPL binary size by about 608 bytes. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: acpi: Add common Intel ACPI tablesSimon Glass2020-09-251-0/+2
| | | | | | | Add various tables that are common to Intel CPUs. These functions can be used by arch-specific CPU code. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: acpi: Add a common routine to write WiFi infoSimon Glass2020-09-251-0/+1
| | | | | | | | | Intel WiFi chips can use a common routine to write the information needed by linux. Add an implementation of this. Enable it for coral. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: apl: Support writing the IntelGraphicsMem tableSimon Glass2020-09-251-0/+4
| | | | | | | This table is needed by the Linux graphics driver to handle graphics correctly. Write it to ACPI. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: coreboot: Allow building an SPL imageSimon Glass2020-05-041-0/+2
| | | | | | | | Make a few adjustments to allow us to build an SPL image for coreboot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move P2SB from Apollo Lake to a more generic locationWolfgang Wallner2020-02-071-0/+1
| | | | | | | | The Primary to Sideband Bridge (P2SB) is not specific to Apollo Lake, so move its driver to a common location within arch/x86. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: itss: Add a Kconfig option to enable/disable ITSS driverWolfgang Wallner2020-02-041-3/+1
| | | | | | | | | | | | | Add a Kconfig option to support enabling/disabling the inclusion of the ITSS driver depending on the platform. Atuomatically select the ITSS driver when building for Apollo Lake. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232761/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move itss.c from Apollo Lake to a more generic locationWolfgang Wallner2020-02-041-0/+3
| | | | | | | | | | | The Interrupt Timer Subsystem (ITSS) is not specific to Apollo Lake, so move it to a common location within arch/x86. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: conditionally build itss.c] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add low-power subsystem (lpss) supportSimon Glass2019-12-151-0/+1
| | | | | | | | | This subsystem is present on various Intel SoCs. Add very basic support for taking an lpss device out of reset. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add support for newer CAR schemesSimon Glass2019-12-151-0/+8
| | | | | | | | | | | Newer Intel SoCs have different ways of setting up cache-as-ram (CAR). Add support for these along with suitable configuration options. To make the code cleaner, adjust a few definitions in processor.h so that they can be used from assembler. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: spi: Add helper functions for Intel Fast SPISimon Glass2019-12-151-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Most x86 CPUs use a mechanism where the SPI flash is mapped into the very top of 32-bit address space, so that it can be executed in place and read simply by copying from memory. For an 8MB ROM the mapping starts at 0xff800000. However some recent Intel CPUs do not use a simple 1:1 memory map. Instead the map starts at a different address and not all of the SPI flash is accessible through the map. This 'Fast SPI' feature requires that U-Boot check the location of the map. It is also possible (optionally) to read from the SPI flash using a driver. Add support for booting from Fast SPI. The memory-mapped version is used by both TPL and SPL on Apollo Lake. In respect of a SPI flash driver, the actual SPI driver is ich.c - this just adds a few helper functions and definitions. This is used by Apollo Lake. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Support TPL in Intel common codeSimon Glass2019-05-081-3/+6
| | | | | | | | Update the Makefie rules to ensure that the correct files are built when TPL is being used. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add common Intel code for SPLSimon Glass2019-05-081-0/+6
| | | | | | | | Add an implementation of arch_cpu_init_f() so that the x86 SPL code builds and identifies the CPU. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Allow 16-bit init to be in TPLSimon Glass2019-05-081-1/+1
| | | | | | | | At present we support having 16-bit init be in SPL or U-Boot proper, but not TPL. Add support for this so that TPL can boot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Rename efi-x86 target to efi-x86_appBin Meng2018-06-171-1/+1
| | | | | | | To avoid confusion, let's rename the efi-x86 target to efi-x86_app. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini2018-05-071-3/+1
| | | | | | | | | | | | | | | | | | | | When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
* x86: Use X86_32BIT_INIT instead of X86_RESET_VECTORSimon Glass2017-02-061-4/+6
| | | | | | | | Use this new option to control the location of 32-bit init. This will allow us to place this in SPL if needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add common SDRAM-init codeSimon Glass2016-03-171-0/+1
| | | | | | | | | The code to call the memory reference code is common to several Intel CPUs. Add common code for performing this init. Intel calls this 'Pre-EFI-Init' (PEI), where EFI stands for Extensible Firmware Interface. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move common PCH code into a common placeSimon Glass2016-03-171-0/+1
| | | | | | | | The SATA indexed register write functions are common to several Intel PCHs. Move this into a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move Intel Management Engine code to a common placeSimon Glass2016-03-171-0/+2
| | | | | | | | | | Some of the Intel ME code is common to several Intel CPUs. Move it into a common location. Add a header file for report_platform.c also. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [squashed in http://patchwork.ozlabs.org/patch/598372/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move common CPU code to its own placeSimon Glass2016-03-171-0/+1
| | | | | | | | Some of the Intel CPU code is common to several Intel CPUs. Move it into a common location along with required declarations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move common LPC code to its own placeSimon Glass2016-03-171-0/+1
| | | | | | | | Some of the LPC code is common to several Intel LPC devices. Move it into a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move microcode code to a common locationSimon Glass2016-03-171-0/+3
| | | | | | | This code is used on several Intel CPUs. Move it into a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move cache-as-RAM code into a common locationSimon Glass2016-03-171-0/+7
This cache-as-RAM (CAR) code is common to several Intel chips. Create a new intel_common directory and move it in there. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
generated by cgit (git 2.34.1) at 2026-01-08 11:58:17 +0000