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* treewide: Convert macro and uses of __section(foo) to __section("foo")Marek Behún2021-05-241-1/+1
| | | | | | | | | | | | | | | | | This commit does the same thing as Linux commit 33def8498fdd. Use a more generic form for __section that requires quotes to avoid complications with clang and gcc differences. Remove the quote operator # from compiler_attributes.h __section macro. Convert all unquoted __section(foo) uses to quoted __section("foo"). Also convert __attribute__((section("foo"))) uses to __section("foo") even if the __attribute__ has multiple list entry forms. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: qemu: move QFW to its own uclassAsherah Connor2021-04-123-48/+21
| | | | | | | | | | | | | We move qfw into its own uclass and split the PIO functions into a specific driver for that uclass. The PIO driver is selected in the qemu-x86 board config (this covers x86 and x86_64). include/qfw.h is cleaned up and documentation added. Signed-off-by: Asherah Connor <ashe@kivikakk.ee> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* x86: coral: Allow init of debug UART in U-Boot properSimon Glass2021-03-273-58/+64
| | | | | | | | | | | At present the debug UART is only set up in SPL, on the assumption that the boot flow will always pass through there. When booting from coreboot, SPL is not used, so the debug UART is not available. Move the code into a common place so that it can be used in U-Boot proper also. Add the required init to start_from_spl.S as well. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: coral: Avoid build error with !CONFIG_ACPIGENSimon Glass2021-03-271-5/+9
| | | | | | | When CONFIG_ACPIGEN is not enabled the CPU code does not build. Fix this by moving things around. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Allow installing an e820 when booting from corebootSimon Glass2021-03-271-26/+1
| | | | | | | | Move this code into a generic location so that it can be used by other x86 boards which want to boot from coreboot. Also ensure that this is called if booting from coreboot. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Move coreboot sysinfo parsing into generic x86 codeSimon Glass2021-03-272-256/+0
| | | | | | | | It is useful to be able to parse coreboot tables on any x86 build which is booted from coreboot. Add a new Kconfig option to enable this feature and move the code so it can be used on any board, if enabled. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Move coreboot timestamp info into coreboot_tables.hSimon Glass2021-03-271-12/+0
| | | | | | | | This all relates to the sysinfo structure provided by coreboot. Put the timestamp definitions into the same file as the others. Tidy up a few comments at the same time. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Make coreboot sysinfo available to any x86 boardSimon Glass2021-03-274-4/+4
| | | | | | | | | It is possible to boot U-Boot for chromebook_coral either 'bare metal' or from coreboot. In the latter case we want to provide access to the coreboot sysinfo tables. Move the definitions into a file available to any x86 board. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: apl: Use read-only SPL and new of-platdataSimon Glass2021-03-261-0/+2
| | | | | | | | With Apollo Lake, SPL is placed in read-only memory. Set this new option so that OF_PLATDATA_INST can be used. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: itss: Tidy up bind() for of-platdata-instSimon Glass2021-03-261-2/+3
| | | | | | | | | | | With the standard of-platdata we must fix up driver_data manually. With of-platadata-inst this is not necessary, since it is added to the device by dtoc. Update the code to handle this. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: apl: Tell of-platdata about a required header fileSimon Glass2021-03-261-0/+1
| | | | | | | | This enum is needed to generate build-time devices. Tell dtoc where to find the header, to avoid compile errors in the generated code. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: apl: Fix the header order in pmcSimon Glass2021-03-261-1/+1
| | | | | | | | | | The dm.h header should come first. In fact it needs to, since otherwise the driver model definitions are not available to dt-structs.h Fix this, since it causes problems with OF_PLATDATA_INST. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Define a region for device priv/plat dataSimon Glass2021-03-261-0/+8
| | | | | | | | Collect this together in one place, so driver model can access set it up in a new place if needed. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge tag 'v2021.04-rc4' into nextTom Rini2021-03-152-1/+2
|\ | | | | | | Prepare v2021.04-rc4
| * x86: Select advanced Intel code only if allowedSimon Glass2021-03-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present most of the Intel-specific code is built on all devices, even those which don't have software support for the features provided there. This means that any board can enable CONFIG_INTEL_ACPIGEN even if it does not have the required features. Add a new INTEL_SOC option to control this access. This must be selected by SoCs that can support the required features. Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: fixed a typo in arch/x86/Kconfig] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: sizeof-array-div error in lpc_common_early_initHeinrich Schuchardt2021-03-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Building qemu-x86_64_defconfig with GCC 11.0 fails with: arch/x86/cpu/intel_common/lpc.c: In function ‘lpc_common_early_init’: arch/x86/cpu/intel_common/lpc.c:56:40: error: expression does not compute the number of elements in this array; element type is ‘struct reg_info’, not ‘u32’ {aka ‘unsigned int’} [-Werror=sizeof-array-div] 56 | sizeof(values) / sizeof(u32)); | ^ arch/x86/cpu/intel_common/lpc.c:56:40: note: add parentheses around the second ‘sizeof’ to silence this warning arch/x86/cpu/intel_common/lpc.c:50:11: note: array ‘values’ declared here 50 | } values[4], *ptr; | ^~~~~~ Add parentheses to silence warning. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | reset: Remove addr parameter from reset_cpu()Harald Seiler2021-03-021-1/+1
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Historically, the reset_cpu() function had an `addr` parameter which was meant to pass in an address of the reset vector location, where the CPU should reset to. This feature is no longer used anywhere in U-Boot as all reset_cpu() implementations now ignore the passed value. Generic code has been added which always calls reset_cpu() with `0` which means this feature can no longer be used easily anyway. Over time, many implementations seem to have "misunderstood" the existence of this parameter as a way to customize/parameterize the reset (e.g. COLD vs WARM resets). As this is not properly supported, the code will almost always not do what it is intended to (because all call-sites just call reset_cpu() with 0). To avoid confusion and to clean up the codebase from unused left-overs of the past, remove the `addr` parameter entirely. Code which intends to support different kinds of resets should be rewritten as a sysreset driver instead. This transformation was done with the following coccinelle patch: @@ expression argvalue; @@ - reset_cpu(argvalue) + reset_cpu() @@ identifier argname; type argtype; @@ - reset_cpu(argtype argname) + reset_cpu(void) { ... } Signed-off-by: Harald Seiler <hws@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge branch '2021-02-02-drop-asm_global_data-when-unused'Tom Rini2021-02-1554-5/+49
|\ | | | | | | - Merge the patch to take <asm/global_data.h> out of <common.h>
| * common: Drop asm/global_data.h from common headerSimon Glass2021-02-0254-5/+49
| | | | | | | | | | | | | | | | | | | | | | | | Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* | x86: qemu: Fix broken multi-core bootBin Meng2021-02-031-0/+6
|/ | | | | | | | | | | | | Unfortunately the multi-core boot for QEMU x86 has been broken since commit 77a5e2d3bc61 ("x86: mp_init: Set up the CPU numbers at the start"). In order to support QEMU x86 multi-core boot, the /cpus node must be bound before any actual fix up in qemu_cpu_fixup(). This adds the uclass_get() call to ensure this, just like what was done before. Fixes: 77a5e2d3bc61 ("x86: mp_init: Set up the CPU numbers at the start") Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: spl: Make moving BSS conditionalSimon Glass2021-02-011-0/+2
| | | | | | | | | At present BSS is always placed in SDRAM. If a separate BSS is not in use this means that BSS doesn't work as expected. Make the setting conditional on the SEPARATE_BSS option. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Make sure the SPL image ends on a suitable boundarySimon Glass2021-02-011-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The part of U-Boot that actually ends up in u-boot-nodtb.bin is not built with any particular alignment. It ends at the start of the BSS section. The BSS section selects its own alignment, which may larger. This means that there can be a gap of a few bytes between the image ending and BSS starting. Since u-boot.bin is build by joining u-boot-nodtb.bin and u-boot.dtb (with perhaps some padding for BSS), the expected result is not obtained. U-Boot uses the end of BSS to find the devicetree, so this means that it cannot be found. Add 32-byte alignment of BSS so that the image size is correct and appending the devicetree will place it at the end of BSS. Example SPL output without this patch: Sections: Idx Name Size VMA LMA File off Algn 0 .text 000142a1 fef40000 fef40000 00001000 2**4 CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE 1 .u_boot_list 000014a4 fef542a8 fef542a8 000152a8 2**3 CONTENTS, ALLOC, LOAD, RELOC, DATA 2 .rodata 0000599c fef55760 fef55760 00016760 2**5 CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA 3 .data 00000970 fef5b100 fef5b100 0001c100 2**5 CONTENTS, ALLOC, LOAD, RELOC, DATA 4 .binman_sym_table 00000020 fef5ba70 fef5ba70 0001ca70 2**2 CONTENTS, ALLOC, LOAD, DATA 5 .bss 00000060 fef5baa0 fef5baa0 00000000 2**5 ALLOC You can see that .bss is aligned to 2**5 (32 bytes). This is because of the mallinfo struct in dlmalloc.c: 17 .bss.current_mallinfo 00000028 00000000 00000000 000004c0 2**5 ALLOC In this case the size of u-boot-spl-nodtb.bin is 0x1ba90. This matches up with the _image_binary_end symbol: fef5ba90 g .binman_sym_table 00000000 _image_binary_end But BSS starts 16 bytes later, at 0xfef5baa0, due to the 32-byte alignment. So we must align _image_binary_end to a 32-byte boundary. This forces the binary size to be 0x1baa0, i.e. ending at the start of bss, as expected. Note that gcc reports __BIGGEST_ALIGNMENT__ of 16 on this build, even though it generates an object file with a member that requests 32-byte alignment. The current_mallinfo struct is 40 bytes in size. Increasing the struct to 68 bytes (i.e. just above a 64-byte boundary) does not cause the alignment to go above 32 bytes. So it seems that 32 bytes is the maximum alignment at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: add more details in the commit message to help people understand] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Enhance debugging in the SPL loaderSimon Glass2021-02-011-5/+7
| | | | | | | | Move to log_debug() and make use of the new SPL function to find the text base. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: acpi_gpe: Update driver name to match devicetreeSimon Glass2021-02-011-2/+4
| | | | | | | | Use a driver name in line with the compatible string so that of-platdata can use this driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: typo segementHeinrich Schuchardt2021-01-302-2/+2
| | | | | | | %s/segement/segment/ Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* Merge tag 'dm-pull-5jan21' of git://git.denx.de/u-boot-dm into nextTom Rini2021-01-0514-123/+78
|\ | | | | | | | | | | | | | | | | Driver model: make some udevice fields private Driver model: Rename U_BOOT_DEVICE et al. dtoc: Tidy up and add more tests ns16550 code clean-up x86 and sandbox minor fixes for of-platdata dtoc prepration for adding build-time instantiation
| * x86: apl: Adjust how the UART gets its platform dataSimon Glass2021-01-051-19/+24
| | | | | | | | | | | | | | | | | | | | | | | | At present this driver calls malloc() to start a new platform data structure, fills it in and tells driver model to use it. We want to avoid malloc, particularly with the new version of of-platdata. Create a new struct which encompasses both the dtd struct and the ns16550 one, to avoid this. Unfortunately we must copy the data into the right place for the ns16550 driver. Add some comments about this. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: apl: Use struct spi_nor instead of struct spi_flashSimon Glass2021-01-051-1/+1
| | | | | | | | | | | | | | | | This construct effectively uses struct spi_nor due to a #define in spi-nor.h so we may as well use that struct here. This allows dtoc to parse it correctly. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Move priv/plat structs for intel_common to headersSimon Glass2021-01-052-27/+1
| | | | | | | | | | | | | | With the new of-platdata, these need to be available to dt_platdata.c so must be in header files. Move them. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: apl: Move priv/plat structs to headersSimon Glass2021-01-052-26/+2
| | | | | | | | | | | | | | With the new of-platdata, these need to be available to dt_platdata.c so must be in header files. Move them. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: apl: Reduce size for TPLSimon Glass2021-01-058-11/+29
| | | | | | | | | | | | | | | | | | | | Update various drivers to use of_match_ptr() and to avoid including debug strings in TPL. Omit the WiFi driver entirely, since it is not used in TPL. This reduces the TPL binary size by about 608 bytes. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: apl: Update hostbridge to remove unwanted TPL codeSimon Glass2021-01-051-5/+9
| | | | | | | | | | | | | | | | | | At present several strings from this file appear in the TPL binary. Add preprocessor checks to drop them. This reduces the TPL binary size by about 128 bytes. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: coral: Move fsp-m settings to a subnodeSimon Glass2021-01-051-1/+4
| | | | | | | | | | | | | | | | | | At present these settings are in the node for host-bridge and so are visible in TPL as well as SPL. But they are only used for SPL. Move them to a subnode so that TPL does not included them. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Move call64 into its own sectionSimon Glass2021-01-051-0/+1
| | | | | | | | | | | | | | When this code is not used (e.g. by TPL) we want it to be excluded from the image. Put it in its own section so that this happens. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: apl: Use const for driver operationsSimon Glass2021-01-052-2/+2
| | | | | | | | | | | | | | Update these declarations to const to ensure that the data ends up in the rodata section. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: Use access methods for dev/uclass private dataSimon Glass2021-01-052-2/+3
| | | | | | | | | | | | | | | | | | | | | | Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
| * x86: apl: Drop support for !OF_PLATDATA_PARENTSimon Glass2021-01-052-28/+1
| | | | | | | | | | | | | | This code was kept around after of-platdata started supporting parent devices. That feature seems stable now, so let's drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
| * serial: Update NS16550_t and struct NS16550Simon Glass2021-01-052-2/+2
| | | | | | | | | | | | | | | | | | | | | | Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
* | Merge tag 'v2021.01-rc5' into nextTom Rini2021-01-052-5/+46
|\ \ | |/ |/| | | | | | | Prepare v2021.01-rc5 Signed-off-by: Tom Rini <trini@konsulko.com>
| * x86: edison: Switch to DM_USB_GADGETAndy Shevchenko2020-12-161-4/+0
| | | | | | | | | | | | | | | | | | | | | | DM is the modern default approach for the drivers in U-Boot. It also allows to configure code via Device Tree. Move Intel Edison to use DM_USB_GADGET and drop hard coded values. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: edison: Use dwc3-generic driver for Intel EdisonAndy Shevchenko2020-12-161-0/+3
| | | | | | | | | | | | | | | | | | Use generic Synopsys DesignWare 3 driver on Intel Edison. For now it's just a stub which allows future refactoring. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: edison: BINMAN selection is specific to the boardAndy Shevchenko2020-12-161-1/+0
| | | | | | | | | | | | | | | | | | | | The platforms based on Intel Tangier may have different requirements how to create bootloader bundle to supply to a device. Currently the BINMAN approach is for Intel Edison only. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: tangier: Find proper memory region for relocationAndy Shevchenko2020-12-161-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It appears that U-Boot works by luck on Intel Edison board because the amount of RAM is less than 1 GB and standard way of calculating the top of it work for this configuration. However, this won't work if the amount of RAM is different and split differently in address space. We have to find the suitable window correctly. Find proper memory region for relocation by scanning MMAP SFI table in board_get_usable_ram_top() callback. According to the address map documentation the Main Memory is guaranteed to lie in the 0..2 GB range, that's why we limit search by this range. Fixes: e71de54a4943 ("x86: Add Intel Tangier support") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: fixed a typo in the commit message] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: Drop unnecessary mp_init logicSimon Glass2020-12-182-17/+8
| | | | | | | | | | | | | | | | | | | | Now that sequence numbers are set up when devices are bound, this code is not needed. Also, we should use dev_seq() instead of req_seq. Update the whole file accordingly. Also fix up APL cpu while we are here. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: Avoid accessing seq directlySimon Glass2020-12-182-2/+2
| | | | | | | | | | | | | | | | | | | | At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: treewide: Rename ..._platdata variables to just ..._platSimon Glass2020-12-1311-38/+38
| | | | | | | | | | | | | | Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: treewide: Update 'auto' declarations to be on one lineSimon Glass2020-12-131-2/+1
| | | | | | | | | | | | | | | | | | Fix up the code style for those declarations that should now fit onto one line, which is all of them that currently do not. This is needed for dtoc to detect the structs correctly, at present. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: treewide: Rename ofdata_to_platdata() to of_to_plat()Simon Glass2020-12-139-19/+19
| | | | | | | | | | | | | | This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: treewide: Rename dev_get_platdata() to dev_get_plat()Simon Glass2020-12-136-13/+13
| | | | | | | | | | | | Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: treewide: Rename 'platdata' variables to just 'plat'Simon Glass2020-12-1311-18/+18
| | | | | | | | | | | | | | | | | | | | We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit (git 2.34.1) at 2025-09-02 18:16:27 +0000