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* riscv: Add exception codes for xcause registerBin Meng2018-12-181-0/+15
* riscv: Add CSR numbersBin Meng2018-12-181-0/+221
* riscv: Remove non-DM version of print_cpuinfo()Bin Meng2018-12-181-37/+0
* riscv: Probe cpus during bootBin Meng2018-12-182-0/+27
* riscv: Enlarge the default SYS_MALLOC_F_LENBin Meng2018-12-181-0/+3
* riscv: qemu: Add platform-specific Kconfig optionsBin Meng2018-12-182-0/+12
* riscv: Implement riscv_get_time() API using rdtime instructionAnup Patel2018-12-183-0/+47
* riscv: Add a SYSCON driver for SiFive's Core Local InterruptorBin Meng2018-12-185-0/+116
* riscv: Introduce a Kconfig option for machine modeAnup Patel2018-12-181-5/+16
* riscv: ax25: Hide the ax25-specific Kconfig optionBin Meng2018-12-182-11/+18
* riscv: qemu: Create a simple-bus driver for the soc nodeBin Meng2018-12-181-0/+14
* riscv: add Kconfig entries for the code modelLukas Auer2018-12-182-1/+26
* riscv: ax25-ae350: Pass dtb address to u-boot with a1 registerRick Chen2018-12-051-2/+0
* riscv: Add kconfig option to run U-Boot in S-modeAnup Patel2018-12-054-17/+48
* riscv: efi: Generate Microsoft PE format compliant imagesBin Meng2018-12-021-6/+6
* riscv: cache: Implement i/dcache [status, enable, disable]Rick Chen2018-11-269-10/+146
* riscv: dts: Add ae350_32.dts for RV32IRick Chen2018-11-263-1/+458
* riscv: dts: Sync to Linux Kernel ae350 dts.Rick Chen2018-11-261-15/+92
* riscv: align bootm implementation with that of other architecturesLukas Auer2018-11-261-27/+70
* riscv: save hart ID and device tree passed by prior boot stageLukas Auer2018-11-262-2/+16
* riscv: do not blindly modify the mstatus CSRLukas Auer2018-11-261-4/+4
* riscv: remove unused labels in start.SLukas Auer2018-11-261-9/+0
* Drop CONFIG_INIT_CRITICALBin Meng2018-11-261-13/+0
* riscv: align mtvec on a 4-byte boundaryLukas Auer2018-11-261-1/+1
* riscv: fix inconsistent use of spaces and tabs in start.SLukas Auer2018-11-261-161/+161
* riscv: implement the invalidate_icache_* functionsLukas Auer2018-11-261-0/+10
* riscv: hang on unhandled exceptionsLukas Auer2018-11-261-0/+2
* riscv: treat undefined exception codes as reservedLukas Auer2018-11-261-2/+6
* riscv: complete the list of exception codesLukas Auer2018-11-261-1/+12
* riscv: do not reimplement generic io functionsLukas Auer2018-11-261-28/+3
* riscv: make use of the barrier functions from LinuxLukas Auer2018-11-262-7/+71
* riscv: fix use of incorrectly sized variablesLukas Auer2018-11-264-11/+15
* riscv: enable -fdata-sectionsLukas Auer2018-11-261-1/+2
* riscv: set -march and -mabi based on the Kconfig configurationLukas Auer2018-11-262-4/+20
* riscv: add Kconfig entries for the C and A ISA extensionsLukas Auer2018-11-261-0/+11
* riscv: select CONFIG_PHYS_64BIT on RV64I systemsLukas Auer2018-11-261-0/+1
* riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64ILukas Auer2018-11-262-9/+9
* Use _AC and UL macros from linux/const.hBaruch Siach2018-11-201-0/+2
* Kbuild: add LDFLAGS_STANDALONEDaniel Schwierzeck2018-11-181-2/+2
* riscv: bootm: Add dm_remove_devices_flags() call to do_bootm_linux()Bin Meng2018-11-141-1/+10
* riscv: allow native compilationHeinrich Schuchardt2018-10-031-4/+0
* riscv: cosmetic: Reword do_reset() printf message.Rick Chen2018-10-031-1/+1
* riscv: Move do_reset() to a common placeBin Meng2018-10-034-17/+18
* riscv: Add QEMU virt board supportBin Meng2018-10-034-0/+56
* riscv: ae350: Clean up mixed tabs and spaces in the dtsBin Meng2018-10-031-87/+90
* riscv: Make start.S available for all targetsBin Meng2018-10-035-4/+4
* riscv: bootm: Pass mhartid CSR value to kernelBin Meng2018-10-031-2/+3
* riscv: Remove CSR read/write defines in encoding.hBin Meng2018-10-031-46/+4
* riscv: Add a helper routine to print CPU informationBin Meng2018-10-034-0/+179
* riscv: Explicitly pass -march and -mabi to the compilerBin Meng2018-10-031-2/+6
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