diff options
| author | Anup Patel <anup@brainfault.org> | 2018-12-12 06:12:31 -0800 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2018-12-18 09:56:27 +0800 |
| commit | 511107d85d6f2739a641076acfb5646ba2a19fc8 (patch) | |
| tree | f71c7e8185c6fe4ae6881e41d811e9d15f25672a /arch/riscv/Kconfig | |
| parent | 644a3cd77e840d1be6a714b8ce284d6ef3ad2f06 (diff) | |
| download | u-boot-511107d85d6f2739a641076acfb5646ba2a19fc8.tar.gz u-boot-511107d85d6f2739a641076acfb5646ba2a19fc8.tar.xz u-boot-511107d85d6f2739a641076acfb5646ba2a19fc8.zip | |
riscv: Implement riscv_get_time() API using rdtime instruction
This adds an implementation of riscv_get_time() API that is using
rdtime instruction.
This is the case for S-mode U-Boot, and is useful for processors
that support rdtime in M-mode too.
Signed-off-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Diffstat (limited to 'arch/riscv/Kconfig')
| -rw-r--r-- | arch/riscv/Kconfig | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index f513f52672..7dc6e3fad2 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -104,4 +104,12 @@ config SIFIVE_CLINT The SiFive CLINT block holds memory-mapped control and status registers associated with software and timer interrupts. +config RISCV_RDTIME + bool + default y if RISCV_SMODE + help + The provides the riscv_get_time() API that is implemented using the + standard rdtime instruction. This is the case for S-mode U-Boot, and + is useful for processors that support rdtime in M-mode too. + endmenu |