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* clk: actions: Add common clock driverAmit Singh Tomar2020-04-244-34/+112
* arm: dts: sync dts for Action Semi S900Amit Singh Tomar2020-04-241-3/+3
* clk: armada-37xx-periph: fix DDR PHY clock divider valuesMarek Behún2020-04-221-2/+2
* clk: imx: add i.IMXRT1020 clk driverGiulio Benetti2020-04-183-0/+244
* clk: imx: clk-imxrt1050: add set_parent() callbackGiulio Benetti2020-04-181-0/+19
* clk: imx: clk-imxrt1050: setup PLL5 for video in non-SPLGiulio Benetti2020-04-181-1/+8
* clk: imx: clk-imxrt1050: fix typo in clock name "video:"Giulio Benetti2020-04-181-1/+1
* clk: imx: pllv3: add enable_bitGiulio Benetti2020-04-181-0/+9
* Merge tag 'arc-fixes-for-2020.07-rc1' of https://gitlab.denx.de/u-boot/custod...Tom Rini2020-04-161-1/+2
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| * ARC: HSDK: CGU: fix tunnel clock calculationEugeniy Paltsev2020-04-161-1/+2
* | dm: core: remove the duplicated function dm_ofnode_pre_relocPatrick Delaunay2020-04-162-2/+2
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* configs: stm32mp1: replace STM32MP1_TRUSTED by TFABOOTPatrick Delaunay2020-04-151-1/+1
* Merge branch 'next'Tom Rini2020-04-134-3/+32
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| * Merge tag 'u-boot-amlogic-20200406' of https://gitlab.denx.de/u-boot/custodia...Tom Rini2020-04-083-0/+22
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| | * clk: meson: reset mmc clock on probeJerome Brunet2020-04-063-0/+21
| | * clk: meson-g12a: missing breakHeinrich Schuchardt2020-04-061-0/+1
| * | Merge tag 'xilinx-for-v2020.07' of https://gitlab.denx.de/u-boot/custodians/u...Tom Rini2020-04-072-1/+9
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| * | clk: stm32mp1: add SPI5_K supportPatrick Delaunay2020-03-241-0/+7
| * | clk: stm32mp1: correct CKSELR masksPatrick Delaunay2020-03-241-3/+3
* | | clk: socfpga: Read the clock parent's register base in probe functionChee Hong Ang2020-04-051-22/+18
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* | clk: rk3399: Set empty for vopl assigned-clocksJagan Teki2020-04-021-0/+7
* | clk: renesas: Switch to fdtdec_get_addr_size_auto_noparent() on Gen2Marek Vasut2020-03-301-1/+2
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* x86: remove dead code in intel_clk_get_rate()Heinrich Schuchardt2020-03-051-4/+0
* versal: drivers: clk: Fix invalid clock name queriesRajan Vaja2020-02-281-0/+6
* Merge tag 'u-boot-stm32-20200214' of https://gitlab.denx.de/u-boot/custodians...Tom Rini2020-02-141-4/+5
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| * clk: stm32mp1: solve type issue in stm32mp1_lse_enable and stm32mp1_clktreePatrick Delaunay2020-02-131-4/+5
* | CLK: HSDK: fix HDMI clock calculationEugeniy Paltsev2020-02-121-10/+21
* | CLK: HSDK: Check for PLL bypass firstlyEugeniy Paltsev2020-02-121-4/+4
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* Merge tag 'dm-pull-6feb20' of https://gitlab.denx.de/u-boot/custodians/u-boot-dmTom Rini2020-02-1147-6/+79
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| * dm: core: Create a new header file for 'compat' featuresSimon Glass2020-02-0530-0/+34
| * dm: core: Require users of devres to include the headerSimon Glass2020-02-0527-1/+40
| * clk: Rename free() to rfree()Simon Glass2020-02-054-5/+5
* | x86: Add a clock driver for Intel devicesSimon Glass2020-02-074-0/+58
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* arm: rockchip: Add common cru.hJagan Teki2020-01-302-39/+39
* clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate()Giulio Benetti2020-01-261-2/+8
* clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate()Giulio Benetti2020-01-261-0/+3
* clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate()Giulio Benetti2020-01-261-2/+8
* clk: Fix error checking of dev_read_addr_ptrSean Anderson2020-01-263-3/+3
* clk: uclass: clk_get_by_name() must not be available if CONFIG_OF_PLATDATA is...Giulio Benetti2020-01-261-1/+1
* clk: show more error info when uclass_get_device_by_namePeng Fan2020-01-261-2/+4
* clk: mediatek: use unsigned type for returning the clk rateFabien Parent2020-01-261-1/+1
* Merge tag '2020-01-20-ti-2020.04' of https://gitlab.denx.de/u-boot/custodians...Tom Rini2020-01-201-2/+1
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| * clk: sci-clk: add slack to clk-set-rate passed to firmwareLokesh Vutla2020-01-201-2/+1
* | common: Move get_tbclk() to time.hSimon Glass2020-01-171-0/+1
* | common: Move clock functions into a new fileSimon Glass2020-01-171-0/+1
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* clk: mediatek: fix clock-rate overflow problemSam Shih2020-01-161-3/+3
* clk: mediatek: add driver for MT7622Sam Shih2020-01-162-0/+679
* clk: fixed_rate: add dummy enable() functionChunfeng Yun2020-01-161-0/+7
* clk: add APIs to get (optional) clock by name without a deviceChunfeng Yun2020-01-161-0/+28
* clk: check valid clock by clk_valid()Chunfeng Yun2020-01-161-8/+8
generated by cgit (git 2.34.1) at 2025-01-10 16:04:26 +0000