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* Merge tag 'u-boot-imx-20210409' of ↵Tom Rini2021-04-091-86/+286
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20210409 ------------------- - Secure Boot : - HAB for MX8M / MX7ULP - CAAM fixes - Fixes for imxrt1020 - Fixes for USDHC driver - Fixes for Toradex (Colibri / Apalis) - Switch to DM for several boards - mx23 olinuxo - usbarmory - marsboard / riotboard - Gateworks GW Ventana - NXP upstream patches (LPDDR / CAAM / HAB) CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/7089
| * imx8m: ddr: Disable CA VREF Training for LPDDR4Ye Li2021-04-081-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Users reported LPDDR4 MR12 value is set to 0 during PHY training, not the value from FSP timing structure, which cause compliance test failed. The root cause is the CATrainOpt[0] is set to 1 in 2D FSP timing but not set in 1D. According to PHY training application node, to enable the feature both 1D and 2D need set this field to 1, otherwise the training result will be incorrect. The PHY training doc also recommends to set CATrainOpt[0] to 0 to use MR12 value from message block (FSP structure). So update the LPDDR4 scripts of all mscale to clear CATrainOpt[0]. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx8mp: refine power on imx8mp boardhaidong.zheng2021-04-081-0/+166
| | | | | | | | | | | | | | | | VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx8mp_evk: Update LPDDR4 refresh timeYe Li2021-04-081-6/+6
| | | | | | | | | | | | | | | | | | Use more safer refresh time value for 6GB LPDDR4 on this EVK board. Update the parameters for every frequency point. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx8mp_evk: Update LPDDR4 timing for new FW 202006Ye Li2021-04-081-90/+99
| | | | | | | | | | | | | | | | | | | | | | After switching to new LPDDR4 firmware 202006 version, have to update the LPDDR4 timing accordingly from RPA tool. Signed-off-by: Ye Li <ye.li@nxp.com> Tested-by: Sherry Sun <sherry.sun@nxp.com> Tested-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx8mp: ddr: Add inline ECC feature supportSherry Sun2021-04-081-0/+27
|/ | | | | | | | Add inline ECC support for lpddr4 on imx8mp-evk. And add a config which can enable/disable inline ECC feature for lpddr4 on imx8mp-evk board. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx8mp: Disables use of MR4 TUF flag (MR4[7]) bitJian Li2020-07-141-1/+1
| | | | | | | | | | In uMCTL2 Databook, for LPDDR4, it is recommended to set this register to 1. This can avoid ddr bandwidth is lower after booting with running for a while. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jian Li <jian.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx8mp: DDR performance tunningJian Li2020-07-141-1/+1
| | | | | | | | | 1. set SCHED.rdwr_idle_gap=0 2. set SCHED.pageclose=1 Reviewed-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Jian Li <jian.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx8mp: enable rd_port_urgentJian Li2020-07-141-0/+1
| | | | | | | Need to enable read urgent for NoC panic signal Signed-off-by: Jian Li <jian.li@nxp.com Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx: add i.MX8MP EVK boardPeng Fan2020-01-081-0/+1847
Add basic i.MX8MP EVK board support U-Boot SPL 2020.01-rc4-00388-gb1bf40c0ae-dirty (Dec 30 2019 - 17:55:33 +0800) power_pca9450b_init DDRINFO: start DRAM init DDRINFO:ddrphy calibration done DDRINFO: ddrmix config done Normal Boot Failed to find clock node. Check device tree WDT: Not found! Trying to boot from BOOTROM image offset 0x8000, pagesize 0x200, ivt offset 0x0 U-Boot 2020.01-rc4-00388-gb1bf40c0ae-dirty (Dec 30 2019 - 17:55:33 +0800) CPU: Freescale i.MX8MP rev1.0 at 1000 MHz Reset cause: POR Model: NXP i.MX8MPlus EVK board DRAM: 6 GiB MMC: FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... OK In: serial Out: serial Err: serial Net: No ethernet found. Hit any key to stop autoboot: 0 u-boot=> mmc list FSL_SDHC: 1 (SD) FSL_SDHC: 2 Signed-off-by: Peng Fan <peng.fan@nxp.com>
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