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* Merge tag 'u-boot-imx-20210409' of ↵Tom Rini2021-04-094-125/+320
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20210409 ------------------- - Secure Boot : - HAB for MX8M / MX7ULP - CAAM fixes - Fixes for imxrt1020 - Fixes for USDHC driver - Fixes for Toradex (Colibri / Apalis) - Switch to DM for several boards - mx23 olinuxo - usbarmory - marsboard / riotboard - Gateworks GW Ventana - NXP upstream patches (LPDDR / CAAM / HAB) CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/7089
| * imx8mp-evk: switch to use binmanPeng Fan2021-04-081-0/+10
| | | | | | | | | | | | Use binman to pack images Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx8m: ddr: Disable CA VREF Training for LPDDR4Ye Li2021-04-081-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Users reported LPDDR4 MR12 value is set to 0 during PHY training, not the value from FSP timing structure, which cause compliance test failed. The root cause is the CATrainOpt[0] is set to 1 in 2D FSP timing but not set in 1D. According to PHY training application node, to enable the feature both 1D and 2D need set this field to 1, otherwise the training result will be incorrect. The PHY training doc also recommends to set CATrainOpt[0] to 0 to use MR12 value from message block (FSP structure). So update the LPDDR4 scripts of all mscale to clear CATrainOpt[0]. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * power: pca9450: add a new parameter for power_pca9450_initPeng Fan2021-04-081-1/+1
| | | | | | | | | | | | | | | | Currently PCA9450 might have address 0x25 or 0x35, so let user choose the address. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| * imx8mp_evk: Increase VDD_ARM to 0.95v Overdrive voltagePeng Fan2021-04-081-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a frequency/timing limitation for SOC and ARM, if SOC is OD voltage/OD freq, then ARM can't run at ND voltage/1.2Ghz, it may have timing risk from SOC to ARM. Current VDD_SOC is set to 0.95v OD voltage in SPL, and kernel will increase bus clocks to OD frequency before it increases ARM voltage. So to conform to the limitation, we'd better increases VDD_ARM to OD voltage in SPL. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx8mp_evk: spl: clean up including headersPeng Fan2021-04-081-13/+4
| | | | | | | | | | | | Clean up the including headers Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx8mp: refine power on imx8mp boardhaidong.zheng2021-04-082-0/+171
| | | | | | | | | | | | | | | | VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx8mp_evk: Update LPDDR4 refresh timeYe Li2021-04-081-6/+6
| | | | | | | | | | | | | | | | | | Use more safer refresh time value for 6GB LPDDR4 on this EVK board. Update the parameters for every frequency point. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx8mp_evk: Update LPDDR4 timing for new FW 202006Ye Li2021-04-081-90/+99
| | | | | | | | | | | | | | | | | | | | | | After switching to new LPDDR4 firmware 202006 version, have to update the LPDDR4 timing accordingly from RPA tool. Signed-off-by: Ye Li <ye.li@nxp.com> Tested-by: Sherry Sun <sherry.sun@nxp.com> Tested-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx8mp: ddr: Add inline ECC feature supportSherry Sun2021-04-081-0/+27
| | | | | | | | | | | | | | | | Add inline ECC support for lpddr4 on imx8mp-evk. And add a config which can enable/disable inline ECC feature for lpddr4 on imx8mp-evk board. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx8mm/p: remove boot.cmdPeng Fan2021-04-081-25/+0
|/ | | | | | These files should not be in U-Boot repo Signed-off-by: Peng Fan <peng.fan@nxp.com>
* common: Drop asm/global_data.h from common headerSimon Glass2021-02-022-0/+2
| | | | | | | | | | | | Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* board: imx8mp: add boot.cmd for distro boot on iMX8MPAlice Guo2021-01-231-0/+25
| | | | | | | | | | | | | | Distro Boot requires a U-Boot-specific script named boot.scr or boot.scr.uimg which contains boot commands to boot the system. The boot.cmd is such a file. Use mkimage to generate boot.scr or boot.scr.uimg from boot.cmd, and the command is: mkimage -A arm -O linux -T script -C none -a 0 -e 0 -n "Distro Boot Script" -d boot.cmd boot.scr.uimg The boot.cmd file is an example script and can be modified based on needs. bootargs is set in this script and root uses the default value "/dev/mmcblk1p2 rootwait rw" which can be changed by overriding mmcroot. Signed-off-by: Alice Guo <alice.guo@nxp.com>
* imx: imx8mp_evk: enable eth supportPeng Fan2021-01-231-1/+64
| | | | | | | Add board code to configure the network interface Add net defconfig Signed-off-by: Peng Fan <peng.fan@nxp.com>
* doc: board: Convert i.MX8MP EVK README to reSTPeng Fan2020-11-011-41/+0
| | | | | | | Convert plain text documentation to reStructuredText format and add it to Sphinx TOC tree. No essential content change. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* board: imx: address dd usage in READMEPeng Fan2020-11-011-1/+1
| | | | | | | | | | | | | | When using cygwin64 "dd (coreutils) 8.26 Packaged by Cygwin (8.26-2)", the last not 512bytes aligned data wat cut off and not burned into SD card. Saying the flash.bin size is 1085608 bytes, not 512bytes aligned. It only burned 1085440 bytes, the leaving 168 bytes were not burnned and cause boot issue. So update README dd command to add "conv=notrunc" Signed-off-by: Peng Fan <peng.fan@nxp.com>
* power: pmic_pca9450: fix PCA9450A I2C addressSébastien Szymanski2020-07-161-1/+1
| | | | | | | | | | | | | | Quoting Ye Li from NXP: "We have confirmed with PMIC team, 0x35 is used only on early chips and not used any more. 0x25 is the final address." Fix it by merging power_pca9450a_init and power_pca9450b_init into one function power_pca9450_init. Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Ye Li <ye.li@nxp.com>
* imx8m: Refactor the OPTEE memory removalPeng Fan2020-07-141-40/+0
| | | | | | | | | | | | | | | Current codes assume the OPTEE address is at the end of first DRAM bank. Adjust the process to allow OPTEE in the middle of first bank. When OPTEE memory is removed from first bank, it may split the first bank to two banks, adjust the MMU table for the split case, Since the default CONFIG_NR_DRAM_BANKS is 4, it is enough, just enlarge i.MX8MP evk to default to avoid issue. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com> Tested-by: Silvano di Ninno <silvano.dininno@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx8mp: Disables use of MR4 TUF flag (MR4[7]) bitJian Li2020-07-141-1/+1
| | | | | | | | | | In uMCTL2 Databook, for LPDDR4, it is recommended to set this register to 1. This can avoid ddr bandwidth is lower after booting with running for a while. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jian Li <jian.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx8mp: DDR performance tunningJian Li2020-07-141-1/+1
| | | | | | | | | 1. set SCHED.rdwr_idle_gap=0 2. set SCHED.pageclose=1 Reviewed-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Jian Li <jian.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx8mp: enable rd_port_urgentJian Li2020-07-141-0/+1
| | | | | | | Need to enable read urgent for NoC panic signal Signed-off-by: Jian Li <jian.li@nxp.com Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx8mp_evk: spl: no need the code since spl framework could do thatPeng Fan2020-06-081-5/+1
| | | | | | | | We no need invoke the code, since spl framework could help us do that. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Fabio Estevam <festevam@gmail.com>
* imx8mp_evk: spl: use spl_early_initPeng Fan2020-06-081-6/+6
| | | | | | | | | Use spl_early_init to replace spl_init, spl_init will be invoked in board_init_r, we only need use spl_early_init to setup malloc and scan early dt. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Fabio Estevam <festevam@gmail.com>
* imx8mp_evk: spl: drop timer_initPeng Fan2020-06-081-2/+0
| | | | | | | | timer_init has been invoked in arch_cpu_init, no need to invoke it again in board code. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Fabio Estevam <festevam@gmail.com>
* imx8mp_evk: spl: drop useless codePeng Fan2020-06-081-14/+0
| | | | | | | | Drop useless getting ccm device, there is no need to explicted do this in board code, and we not enable SPL CLK currently. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Fabio Estevam <festevam@gmail.com>
* imx8mp_evk: Add a README fileFabio Estevam2020-06-081-0/+41
| | | | | | Add a README file explaining the U-Boot build and SD card flash procedures. Signed-off-by: Fabio Estevam <festevam@gmail.com>
* common: Drop log.h from common headerSimon Glass2020-05-181-0/+1
| | | | | | Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* command: Remove the cmd_tbl_t typedefSimon Glass2020-05-182-0/+2
| | | | | | | | | | | | | We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop init.h from common headerSimon Glass2020-05-182-0/+2
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop image.h from common headerSimon Glass2020-05-181-0/+1
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* imx8mp_evk: Remove unrelated commentFabio Estevam2020-05-011-1/+0
| | | | | | | The comment does not relate to the setup_i2c() function, so just remove it. Signed-off-by: Fabio Estevam <festevam@gmail.com>
* imx: imx8m*: Remove do_reset from board filesClaudius Heine2020-05-011-9/+0
| | | | | | | | | | | | | | | | | Use the `do_reset` implementation of `arch/arm/lib/reset.c` in SPL instead. It is very close to what is done here, anyway, and plays more nicely with the rest of U-Boot than adding a custom `do_reset` implementation into board files. `do_reset` from `arch/arm/lib/reset.c` calls `reset_cpu` with 0 as the addr parameter while the boards are passing WDOG1_BASE_ADDR. This is ok because the `reset_cpu` implementation uses WDOG1_BASE_ADDR by default if 0 is passed in. Co-Authored-by: Harald Seiler <hws@denx.de> Signed-off-by: Claudius Heine <ch@denx.de> Signed-off-by: Harald Seiler <hws@denx.de> Reviewed-by: Marek Vasut <marex@denx.de>
* common: Move hang() to the same header as panic()Simon Glass2020-01-171-0/+1
| | | | | | | | | | At present panic() is in the vsprintf.h header file. That does not seem like an obvious choice for hang(), even though it relates to panic(). So let's put hang() in its own header. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Migrate a few more files] Signed-off-by: Tom Rini <trini@konsulko.com>
* common: Move reset_cpu() to the CPU headerSimon Glass2020-01-171-0/+1
| | | | | | Move this function out of common.h and into a relevant header file. Signed-off-by: Simon Glass <sjg@chromium.org>
* imx: add i.MX8MP EVK boardPeng Fan2020-01-086-0/+2131
Add basic i.MX8MP EVK board support U-Boot SPL 2020.01-rc4-00388-gb1bf40c0ae-dirty (Dec 30 2019 - 17:55:33 +0800) power_pca9450b_init DDRINFO: start DRAM init DDRINFO:ddrphy calibration done DDRINFO: ddrmix config done Normal Boot Failed to find clock node. Check device tree WDT: Not found! Trying to boot from BOOTROM image offset 0x8000, pagesize 0x200, ivt offset 0x0 U-Boot 2020.01-rc4-00388-gb1bf40c0ae-dirty (Dec 30 2019 - 17:55:33 +0800) CPU: Freescale i.MX8MP rev1.0 at 1000 MHz Reset cause: POR Model: NXP i.MX8MPlus EVK board DRAM: 6 GiB MMC: FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... OK In: serial Out: serial Err: serial Net: No ethernet found. Hit any key to stop autoboot: 0 u-boot=> mmc list FSL_SDHC: 1 (SD) FSL_SDHC: 2 Signed-off-by: Peng Fan <peng.fan@nxp.com>
generated by cgit (git 2.34.1) at 2025-01-30 17:59:52 +0000