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* x86: apl: Add LPC driverSimon Glass2019-12-153-0/+205
* x86: apl: Add ITSS driverSimon Glass2019-12-153-0/+258
* x86: apl: Add hostbridge driverSimon Glass2019-12-152-0/+180
* x86: apl: Add systemagent driverSimon Glass2019-12-153-0/+62
* x86: apl: Add pinctrl driverSimon Glass2019-12-151-0/+485
* x86: apl: Add UART driverSimon Glass2019-12-153-0/+154
* x86: apl: Add PMC driverSimon Glass2019-12-153-0/+240
* x86: apl: Add basic IO addressesSimon Glass2019-12-151-0/+29
* x86: Move qemu CPU fixup function into its own fileSimon Glass2019-12-153-68/+79
* x86: Add a generic Intel pinctrl driverSimon Glass2019-12-152-0/+679
* x86: Add low-power subsystem (lpss) supportSimon Glass2019-12-153-0/+81
* x86: Make MSR_PKG_POWER_SKU commonSimon Glass2019-12-153-3/+8
* x86: Separate out U-Boot and device tree in ROM imageSimon Glass2019-12-151-3/+11
* x86: Don't repeat microcode in U-Boot if not neededSimon Glass2019-12-151-0/+7
* x86: Add an fdtmap and image-headerSimon Glass2019-12-151-0/+5
* x86: Add an option to control the position of SPLSimon Glass2019-12-152-2/+7
* x86: Add an option to control the position of U-BootSimon Glass2019-12-152-15/+8
* x86: Update .dtsi file for FSP2Simon Glass2019-12-151-1/+31
* x86: Disable microcode section for FSP2Simon Glass2019-12-152-0/+11
* x86: Add support for newer CAR schemesSimon Glass2019-12-155-7/+564
* x86: Add an option to include a FITSimon Glass2019-12-152-0/+14
* x86: Don't include the BIOS emulator in TPLSimon Glass2019-12-151-0/+2
* x86: fsp: Make the notify API call commonSimon Glass2019-12-152-18/+27
* x86: fsp: Allow remembering the location of FSP-SSimon Glass2019-12-151-0/+3
* x86: fsp: Set up an MTRR for the graphics frame bufferSimon Glass2019-12-151-0/+4
* x86: fsp: Add FSP2 base supportSimon Glass2019-12-1510-2/+784
* x86: fsp: Correct wrong header inlude in fsp_support.cSimon Glass2019-12-151-1/+1
* x86: fsp: Make graphics support common to FSP1/2Simon Glass2019-12-153-2/+4
* x86: Allow interrupt to happen onceSimon Glass2019-12-153-9/+11
* x86: Set up the MTRR for SDRAMSimon Glass2019-12-151-0/+5
* x86: Set the DRAM banks to reflect real locationSimon Glass2019-12-151-1/+29
* x86: Move fsp_prepare_mrc_cache() to fsp1 directorySimon Glass2019-12-153-27/+20
* x86: Don't export mrccache_update()Simon Glass2019-12-152-17/+14
* x86: Add mrccache support for a 'variable' cacheSimon Glass2019-12-152-1/+3
* x86: Update mrccache to support multiple cachesSimon Glass2019-12-158-48/+106
* x86: Tidy up error handling in mrccache_save()Simon Glass2019-12-151-12/+7
* x86: Add a new global_data member for the cache recordSimon Glass2019-12-152-6/+7
* x86: Adjust mrccache_get_region() to support get_mmap()Simon Glass2019-12-151-4/+14
* x86: Adjust mrccache_get_region() to use livetreeSimon Glass2019-12-151-29/+26
* x86: Correct mrccache find_next_mrc_cache() calculationSimon Glass2019-12-151-4/+14
* x86: Reduce mrccache record alignment sizeSimon Glass2019-12-151-1/+1
* x86: Define the SPL image startSimon Glass2019-12-151-1/+4
* x86: Move UCLASS_IRQ into a separate fileSimon Glass2019-12-151-5/+0
* x86: Drop unnecessary interrupt code for TPLSimon Glass2019-12-151-0/+2
* x86: Drop unnecessary cpu code for TPLSimon Glass2019-12-152-4/+41
* x86: timer: use a timer base of 0Simon Glass2019-12-152-0/+2
* x86: spi: Add helper functions for Intel Fast SPISimon Glass2019-12-154-0/+143
* i2c: designware: Avoid using static dataSimon Glass2019-12-151-0/+1
* x86: simplify ljmp to 32-bit codeMasahiro Yamada2019-12-081-3/+1
* x86: use data32 directive instead of macro for operand-size prefixMasahiro Yamada2019-12-081-5/+3
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