diff options
| author | Simon Glass <sjg@chromium.org> | 2019-12-08 17:32:10 -0700 |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2019-12-15 11:44:27 +0800 |
| commit | bd47209743341bf68f44cf1bcaa7d797aedd914c (patch) | |
| tree | 31bc8302f165edeab430fa9f05cfc96a0a2913d0 /arch/x86 | |
| parent | 070a94600855d895e3aef97a0acfbf4d8fca26e8 (diff) | |
| download | u-boot-bd47209743341bf68f44cf1bcaa7d797aedd914c.tar.gz u-boot-bd47209743341bf68f44cf1bcaa7d797aedd914c.tar.xz u-boot-bd47209743341bf68f44cf1bcaa7d797aedd914c.zip | |
x86: apl: Add systemagent driver
This driver handles communication with the systemagent which needs to be
told when U-Boot has completed its init.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86')
| -rw-r--r-- | arch/x86/cpu/apollolake/Makefile | 2 | ||||
| -rw-r--r-- | arch/x86/cpu/apollolake/systemagent.c | 23 | ||||
| -rw-r--r-- | arch/x86/include/asm/arch-apollolake/systemagent.h | 37 |
3 files changed, 62 insertions, 0 deletions
diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile index fdda748ea3..3a8c2f66a3 100644 --- a/arch/x86/cpu/apollolake/Makefile +++ b/arch/x86/cpu/apollolake/Makefile @@ -2,5 +2,7 @@ # # Copyright 2019 Google LLC +obj-$(CONFIG_SPL_BUILD) += systemagent.o + obj-y += pmc.o obj-y += uart.o diff --git a/arch/x86/cpu/apollolake/systemagent.c b/arch/x86/cpu/apollolake/systemagent.c new file mode 100644 index 0000000000..b6bc2ba14f --- /dev/null +++ b/arch/x86/cpu/apollolake/systemagent.c @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 Intel Corporation. + * Take from coreboot project file of the same name + */ + +#include <common.h> +#include <asm/intel_regs.h> +#include <asm/io.h> +#include <asm/arch/systemagent.h> + +void enable_bios_reset_cpl(void) +{ + /* + * Set bits 0+1 of BIOS_RESET_CPL to indicate to the CPU + * that BIOS has initialised memory and power management + * + * The FSP-S does not do this. If we leave this as zero then I believe + * the power-aware interrupts don't work in Linux, and CPU 0 always gets + * the interrupt. + */ + setbits_8(MCHBAR_REG(BIOS_RESET_CPL), 3); +} diff --git a/arch/x86/include/asm/arch-apollolake/systemagent.h b/arch/x86/include/asm/arch-apollolake/systemagent.h new file mode 100644 index 0000000000..206d8903fa --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/systemagent.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2017 Intel Corporation. + * Take from coreboot project file of the same name + */ + +#ifndef _ASM_ARCH_SYSTEMAGENT_H +#define _ASM_ARCH_SYSTEMAGENT_H + +/* Device 0:0.0 PCI configuration space */ +#define MCHBAR 0x48 + +/* RAPL Package Power Limit register under MCHBAR */ +#define PUNIT_THERMAL_DEVICE_IRQ 0x700C +#define PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER 0x18 +#define PUINT_THERMAL_DEVICE_IRQ_LOCK 0x80000000 +#define BIOS_RESET_CPL 0x7078 +#define PCODE_INIT_DONE BIT(8) +#define MCHBAR_RAPL_PPL 0x70A8 +#define CORE_DISABLE_MASK 0x7168 +#define CAPID0_A 0xE4 +#define VTD_DISABLE BIT(23) +#define DEFVTBAR 0x6c80 +#define GFXVTBAR 0x6c88 +#define VTBAR_ENABLED 0x01 +#define VTBAR_MASK GENMASK_ULL(39, 12) +#define VTBAR_SIZE 0x1000 + +/** + * enable_bios_reset_cpl() - Tell the system agent that memory/power are ready + * + * This should be called when U-Boot has set up the memory and power + * management. + */ +void enable_bios_reset_cpl(void); + +#endif |