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* common: Drop asm/global_data.h from common headerSimon Glass2021-02-023-1/+2
| | | | | | | | | | | | Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* x86: typo segementHeinrich Schuchardt2021-01-301-1/+1
| | | | | | | %s/segement/segment/ Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move call64 into its own sectionSimon Glass2021-01-051-0/+1
| | | | | | | When this code is not used (e.g. by TPL) we want it to be excluded from the image. Put it in its own section so that this happens. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Show the interrupt pointer with 'irqinfo'Simon Glass2020-11-061-7/+7
| | | | | | | | It is useful for this command to show the address of the interrupt table. Add support for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: cpu: Report address width from cpu_get_info()Simon Glass2020-09-251-0/+23
| | | | | | | Add support for this new field in the common code used by most x86 CPU drivers. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: cpu: Remove unnecessary #ifdefsSimon Glass2020-07-201-2/+0
| | | | | | | | | Drop some #ifdefs that are not needed or can be converted to compile-time checks. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move MP code into mp_initSimon Glass2020-07-201-19/+5
| | | | | | | | | | | At present the 'flight plan' for CPUs is passed into mp_init. But it is always the same. Move it into the mp_init file so everything is in one place. Also drop the SMI function since it does nothing. If we implement SMIs, more refactoring will be needed anyway. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Store the coreboot table address in global_dataSimon Glass2020-07-171-1/+6
| | | | | | | | | | | | | At present this information is used to locate and parse the tables but is not stored. Store it so that we can display it to the user, e.g. with the 'bdinfo' command. Note that now the GD_FLG_SKIP_LL_INIT flag is set in get_coreboot_info(), so it is always set when booting from coreboot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
* x86: fsp: Reinit the FPU after FSP meminitSimon Glass2020-07-091-0/+5
| | | | | | | | | | | | The APL FSP appears to leave the FPU in a bad state in that it has registers in use. This causes an error when the next FPU operation is performed. Work around this by re-resetting the FPU after calling FSP-M. This allows the freetype console to work correctly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* common: Drop asm/ptrace.h from common headerSimon Glass2020-05-181-0/+1
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Move work-around out of cpu_jump_to_64bit_uboot()Simon Glass2020-05-041-10/+0
| | | | | | | | | | | | | | At present this function copies U-Boot from the last 1MB of ROM. This is not the right way to do it. Instead, the binman symbol should provide the location. But in any case the code should live in the caller, spl_board_load_image(), so that the 64-bit jump function can be used elsewhere. Move it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move coreboot-table detection to common 32/64-bit codeSimon Glass2020-05-041-25/+1
| | | | | | | | | At present this function is only available in 32-bit code. Move it to the common cpu file so it can be used by 64-bit U-Boot too. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add a way to detect running from corebootSimon Glass2020-04-301-0/+2
| | | | | | | | If U-Boot is running from coreboot we need to skip low-level init. Add an way to detect this and to set the gd flag. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move coreboot-table detection into common codeSimon Glass2020-04-301-0/+25
| | | | | | | | | | | To support detecting booting from coreboot, move the code which locates the coreboot tables into a common place. Adjust the algorithm slightly to use a word comparison instead of string, since it is faster. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the comments to 960KB] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: cpu: Skip init code when chain loadingSimon Glass2020-04-301-2/+4
| | | | | | | | | When U-Boot is not the first-stage bootloader the interrupt and cache init must be skipped, as well as init for various peripherals. Update the code to add checks for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Give each driver an IRQ typeSimon Glass2020-02-071-1/+2
| | | | | | | | Add an IRQ type to each driver and use irq_first_device_type() to find and probe the correct one. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: limit the fs segment to the pointer sizeMasahiro Yamada2020-02-041-3/+7
| | | | | | | | | | | | | | | | The fs segment is only used to get the global data pointer. If it is accessed beyond sizeof(new_gd->arch.gd_addr), it is a bug. To specify the byte-granule limit size, drop the G bit, so the flag field is 0x8093 instead of 0xc093, and set the limit field to sizeof(new_gd->arch.gd_addr) - 1. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: fixed the comments about FS segement] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* common: Move hang() to the same header as panic()Simon Glass2020-01-171-0/+1
| | | | | | | | | | At present panic() is in the vsprintf.h header file. That does not seem like an obvious choice for hang(), even though it relates to panic(). So let's put hang() in its own header. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Migrate a few more files] Signed-off-by: Tom Rini <trini@konsulko.com>
* common: Move ll_boot_init() to init.hSimon Glass2020-01-172-0/+2
| | | | | | This is an init-related function so belongs in that file. Move it. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Drop unnecessary interrupt code for TPLSimon Glass2019-12-151-0/+2
| | | | | | | | We don't expect an exception in TPL and don't need to set up interrupts in TPL. Drop this whole file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Drop unnecessary cpu code for TPLSimon Glass2019-12-151-4/+37
| | | | | | | | | | We don't need to know every detail about the CPU in TPL. Drop some superfluous functions to reduce code size. Add a simple CPU detection algorithm which just supports Intel and AMD, since we only support TPL on Intel, so far. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* common: Move interrupt functions into a new headerSimon Glass2019-12-021-0/+1
| | | | | | | | | | | | These functions do not use driver model but are fairly widely used in U-Boot. But it is not clear that they will use driver model anytime soon, so we don't want to label them as 'legacy'. Move them to a new irq_func.h header file. Avoid the name 'irq.h' since it is widely used in U-Boot already. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* common: Move some cache and MMU functions out of common.hSimon Glass2019-12-021-0/+1
| | | | | | | | | | | | These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* x86: Add a CPU init function for TPLSimon Glass2019-11-031-0/+8
| | | | | | | | For TPL we only need to set up the features and identify the CPU to a basic level. Add a function to handle that. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: show UEFI images involved in crashHeinrich Schuchardt2019-09-101-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If a crash occurs, show the loaded UEFI images to facilitate analysis. This is an example output: => bootefi 0x1000000 Found 0 disks Hello world of bugs! Invalid Opcode (Undefined Opcode) EIP: 0010:[<06ceb06e>] EFLAGS: 00010206 Original EIP :[<fec9906e>] EAX: 00000000 EBX: 06cec000 ECX: 00000fd0 EDX: 00000001 ESI: 06ced18a EDI: 07d0fe10 EBP: 07fe27a0 ESP: 07d0fde0 DS: 0018 ES: 0018 FS: 0020 GS: 0018 SS: 0018 CR0: 00000033 CR2: 00000000 CR3: 00000000 CR4: 00000000 DR0: 00000000 DR1: 00000000 DR2: 00000000 DR3: 00000000 DR6: ffff0ff0 DR7: 00000400 Stack: 0x07d0fde8 : 0x00000000 0x07d0fde4 : 0x06ced040 --->0x07d0fde0 : 0x07fe27a0 0x07d0fddc : 0x00010206 0x07d0fdd8 : 0x00000010 0x07d0fdd4 : 0x06ceb06e UEFI image [0x06cea000:0x06cf0fff] pc=0x106e '/bug-i386.efi' ### ERROR ### Please RESET the board ### With the additional information provided by this patch we know that the problem occurred 0x106e after the load address of bug-i386.efi. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* Fix spelling of available.Vagrant Cascadian2019-05-091-1/+1
| | | | Signed-off-by: Vagrant Cascadian <vagrant@debian.org>
* x86: Add a way to reinit the cpuSimon Glass2019-05-081-44/+69
| | | | | | | | | We cannot init the CPU fully both than once during a boot. Add a new function which can be called to figure out the CPU identity, but which does not change anything. For x86_64, this is empty for now. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Use the existing GDT in the ROM for 64-bit U-Boot properBin Meng2019-02-121-14/+0
| | | | | | | | | | It is unnecessary to use a RAM version GDT for 64-bit U-Boot proper. In fact we can just use the ROM version directly, which not only eliminates the risk of being overwritten by application, but also removes the complexity of patching the cpu_call64(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Don't copy the cpu_call64() function to a hardcoded addressBin Meng2019-02-122-3/+12
| | | | | | | | | | Before jumping to 64-bit U-Boot proper, SPL copies the cpu_call64() function to a hardcoded address 0x3000000. This can have potential conflicts with application usage. Switch the destination address to be allocated from the heap to avoid such risk. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Change 4-level page table base address to low memoryBin Meng2019-02-121-4/+2
| | | | | | | | | | | | | | At present the 4-level page table base address for 64-bit U-Boot proper is assigned an address that conflicts with CONFIG_LOADADDR. Change it to an address within the low memory range instead. Fixes crashes seen when 'dhcp' on QEMU x86_64 with "-net nic -net user,tftp=.,bootfile=u-boot". Reported-by: Alexander Graf <agraf@suse.de> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: make the LAPIC / IOAPIC construct switchable with KconfigHannes Schmelzer2018-12-101-0/+2
| | | | | | | | | | | | There are still systems running which do not have any LAPIC or even IOAPIC. Responsible MSRs for those do not exist and the systems are crashing on trying to setup LAPIC. This commit makes the APIC stuff able to switch off for those boards which dont' have an LAPIC / IOAPIC. Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini2018-05-074-8/+4
| | | | | | | | | | | | | | | | | | | | When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
* x86: Force 32-bit jumps in interrupt handlersJ. Tang2017-02-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Depending upon the compiler used, IRQ entries could vary in sizes. With GCC 5.x, the code generator will use short jumps for some IRQ entries but near jumps for others. For example, GCC 5.4.0 generates the following: $ objdump -d interrupt.o <snip> 00000207 <irq_18>: 207: 6a 12 push $0x12 209: eb 85 jmp 190 <irq_common_entry> 0000020b <irq_19>: 20b: 6a 13 push $0x13 20d: eb 81 jmp 190 <irq_common_entry> 0000020f <irq_20>: 20f: 6a 14 push $0x14 211: e9 7a ff ff ff jmp 190 <irq_common_entry> 00000216 <irq_21>: 216: 6a 15 push $0x15 218: e9 73 ff ff ff jmp 190 <irq_common_entry> This causes a problem in cpu_init_interrupts(), because the IDT setup assumed same sizes for all IRQ entries. GCC 4.x always generated 32-bit jumps, so this previously was not a problem. The fix is to force 32-bit near jumps for all entries within the inline assembly. This works for GCC 5.x, and 4.x was already using that form of jumping. Signed-off-by: Jason Tang <tang@jtang.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move setjmp to the i386 directorySimon Glass2017-02-072-0/+62
| | | | | | | | This code is only used in 32-bit mode. Move it so that it does not get built with 64-bit U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move call64 to the i386 directorySimon Glass2017-02-072-0/+97
| | | | | | | | This code is only used in 32-bit mode. Move it so that it does not get built with 64-bit U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Support jumping from SPL to U-BootSimon Glass2017-02-061-0/+64
| | | | | | | | Add a rough function to handle jumping from 32-bit SPL to 64-bit U-Boot. This still needs work to clean it up. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Fix up CONFIG_X86_64 checkSimon Glass2017-02-061-1/+1
| | | | | | | | When SPL and U-Boot proper have different settings for this flag, we need to use the correct one. Fix this up in the interrupt code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move the i386 code into its own directorySimon Glass2017-02-063-0/+1156
Much of the cpu and interrupt code cannot be compiled on 64-bit x86. Move it into its own directory and build it only in 32-bit mode. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
generated by cgit (git 2.34.1) at 2024-09-20 19:17:55 +0000