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* x86: coral: Allow init of debug UART in U-Boot properSimon Glass2021-03-272-58/+60
| | | | | | | | | | | At present the debug UART is only set up in SPL, on the assumption that the boot flow will always pass through there. When booting from coreboot, SPL is not used, so the debug UART is not available. Move the code into a common place so that it can be used in U-Boot proper also. Add the required init to start_from_spl.S as well. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: coral: Avoid build error with !CONFIG_ACPIGENSimon Glass2021-03-271-5/+9
| | | | | | | When CONFIG_ACPIGEN is not enabled the CPU code does not build. Fix this by moving things around. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: apl: Use read-only SPL and new of-platdataSimon Glass2021-03-261-0/+2
| | | | | | | | With Apollo Lake, SPL is placed in read-only memory. Set this new option so that OF_PLATDATA_INST can be used. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: apl: Tell of-platdata about a required header fileSimon Glass2021-03-261-0/+1
| | | | | | | | This enum is needed to generate build-time devices. Tell dtoc where to find the header, to avoid compile errors in the generated code. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: apl: Fix the header order in pmcSimon Glass2021-03-261-1/+1
| | | | | | | | | | The dm.h header should come first. In fact it needs to, since otherwise the driver model definitions are not available to dt-structs.h Fix this, since it causes problems with OF_PLATDATA_INST. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Select advanced Intel code only if allowedSimon Glass2021-03-091-0/+1
| | | | | | | | | | | | | | | | | At present most of the Intel-specific code is built on all devices, even those which don't have software support for the features provided there. This means that any board can enable CONFIG_INTEL_ACPIGEN even if it does not have the required features. Add a new INTEL_SOC option to control this access. This must be selected by SoCs that can support the required features. Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: fixed a typo in arch/x86/Kconfig] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* common: Drop asm/global_data.h from common headerSimon Glass2021-02-023-0/+3
| | | | | | | | | | | | Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* x86: apl: Enhance debugging in the SPL loaderSimon Glass2021-02-011-5/+7
| | | | | | | | Move to log_debug() and make use of the new SPL function to find the text base. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Adjust how the UART gets its platform dataSimon Glass2021-01-051-19/+24
| | | | | | | | | | | | At present this driver calls malloc() to start a new platform data structure, fills it in and tells driver model to use it. We want to avoid malloc, particularly with the new version of of-platdata. Create a new struct which encompasses both the dtd struct and the ns16550 one, to avoid this. Unfortunately we must copy the data into the right place for the ns16550 driver. Add some comments about this. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: apl: Use struct spi_nor instead of struct spi_flashSimon Glass2021-01-051-1/+1
| | | | | | | | This construct effectively uses struct spi_nor due to a #define in spi-nor.h so we may as well use that struct here. This allows dtoc to parse it correctly. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: apl: Move priv/plat structs to headersSimon Glass2021-01-052-26/+2
| | | | | | | With the new of-platdata, these need to be available to dt_platdata.c so must be in header files. Move them. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: apl: Reduce size for TPLSimon Glass2021-01-054-8/+17
| | | | | | | | | | Update various drivers to use of_match_ptr() and to avoid including debug strings in TPL. Omit the WiFi driver entirely, since it is not used in TPL. This reduces the TPL binary size by about 608 bytes. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: apl: Update hostbridge to remove unwanted TPL codeSimon Glass2021-01-051-5/+9
| | | | | | | | | At present several strings from this file appear in the TPL binary. Add preprocessor checks to drop them. This reduces the TPL binary size by about 128 bytes. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: coral: Move fsp-m settings to a subnodeSimon Glass2021-01-051-1/+4
| | | | | | | | | At present these settings are in the node for host-bridge and so are visible in TPL as well as SPL. But they are only used for SPL. Move them to a subnode so that TPL does not included them. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: apl: Use const for driver operationsSimon Glass2021-01-051-1/+1
| | | | | | | Update these declarations to const to ensure that the data ends up in the rodata section. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: Use access methods for dev/uclass private dataSimon Glass2021-01-051-1/+2
| | | | | | | | | | | Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
* x86: apl: Drop support for !OF_PLATDATA_PARENTSimon Glass2021-01-052-28/+1
| | | | | | | This code was kept around after of-platdata started supporting parent devices. That feature seems stable now, so let's drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
* serial: Update NS16550_t and struct NS16550Simon Glass2021-01-051-1/+1
| | | | | | | | | | | Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
* x86: Drop unnecessary mp_init logicSimon Glass2020-12-181-1/+1
| | | | | | | | | | Now that sequence numbers are set up when devices are bound, this code is not needed. Also, we should use dev_seq() instead of req_seq. Update the whole file accordingly. Also fix up APL cpu while we are here. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: treewide: Rename ..._platdata variables to just ..._platSimon Glass2020-12-134-18/+18
| | | | | | | Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: treewide: Rename ofdata_to_platdata() to of_to_plat()Simon Glass2020-12-133-7/+7
| | | | | | | This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: treewide: Rename dev_get_platdata() to dev_get_plat()Simon Glass2020-12-133-7/+7
| | | | | | Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: treewide: Rename 'platdata' variables to just 'plat'Simon Glass2020-12-134-7/+7
| | | | | | | | | | We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: treewide: Rename auto_alloc_size members to be shorterSimon Glass2020-12-134-5/+5
| | | | | | | | | | | | This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: Remove uses of device_bind_offset()Simon Glass2020-12-131-1/+1
| | | | | | | This function is not needed since the standard device_bind() can be used instead. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: core: Rename device_bind() to device_bind_offset()Simon Glass2020-12-131-1/+1
| | | | | | | | | This function is not necessary anymore, since device_bind_ofnode() does the same thing and works with both flattree and livetree. Rename it to indicate that it is special. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Silence some logging statementsSimon Glass2020-11-061-4/+4
| | | | | | | | Quite a few log_info() calls are included in the x86 code which should use log_debug() instead. Convert them to reduce unwanted output. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Set up Chrome OS to boot into developer modeSimon Glass2020-11-061-6/+20
| | | | | | | | Set up a few fields necessarily to make Chrome OS boot without showing a firmware error. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Use CONFIG_CHROMEOS_VBOOT for verified bootSimon Glass2020-11-061-1/+2
| | | | | | | | | | | | | | | At present CONFIG_CHROMEOS is used to determine whether verified boot is in use. The code to implement that is not in U-Boot mainline. However, it is useful to be able to boot a Chromebook in developer mode in U-Boot mainline without needing the verified boot code. To allow this, use CONFIG_CHROMEOS_VBOOT to indicate that verified boot should be used, and CONFIG_CHROMEOS to indicate that the board supports Chrome OS. That allows us to define CONFIG_CHROMEOS on coral. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Add core init for the SoCSimon Glass2020-11-053-20/+109
| | | | | | | | Set up MSRs required for Apollo Lake. This enables Linux to use the timers correctly. Also write the fixed MSRs for this platform. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Fix up driver names to avoid dtoc warningsSimon Glass2020-11-057-10/+10
| | | | | | | | | | | | At present there are a lot of dtoc warnings reported when building chromebook_coral, of the form: WARNING: the driver intel_apl_lpc was not found in the driver list Correct these by using driver names that matches their compatible string. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Take advantage of the of-platdata parent supportSimon Glass2020-10-291-1/+2
| | | | | | | | Now that parent devices are supported with of-platadata, we don't need the messy code to fix up the parent pointers and allocations on Apollo Lake. Put the code behind a condition. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: apl: Enable SPI flash in TPL with APL_SPI_FLASH_BOOTSimon Glass2020-10-291-0/+2
| | | | | | | | At present, enabling CONFIG_APL_SPI_FLASH_BOOT does not build since SPI and SPI flash are not enabled for TPL. Add a condition to fix this and tidy up a build warning in the SPI-flash driver. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: apl: Check low-level init in FSP-S pre-initSimon Glass2020-09-251-0/+2
| | | | | | | If U-Boot is not running FSP-S it should not do the pre-init either. Add a condition to handle this. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: apl: Drop unnecessary code in PMC driverSimon Glass2020-09-251-6/+2
| | | | | | | We don't have CONFIG_PCI in TPL but it is present in SPL, etc. So this code is not needed. Drop it, and fix a code-style nit just above. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: apl: Generate ACPI table for LPCSimon Glass2020-09-251-0/+18
| | | | | | Add an ACPI table for the LPC on Apollo Lake. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: apl: Generate CPU tablesSimon Glass2020-09-251-0/+77
| | | | | | Add ACPI generation to the APL CPU driver. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: apl: Add support for hostbridge ACPI generationSimon Glass2020-09-251-9/+211
| | | | | | | Support generating a DMAR table and add a few helper routines as well. Also set up NHLT so that audio works. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: apl: Generate required ACPI tablesSimon Glass2020-09-252-0/+212
| | | | | | | Add support for generating various ACPI tables for Apollo Lake. Add a few S3 definitions that are needed. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: apl: Allow reading hostbridge base addressesSimon Glass2020-09-251-0/+27
| | | | | | | Add a few functions to permit reading of various useful base addresses provided by the hostbridge. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Support Atom SoCs using SWSMISCI rather than the SWSCISimon Glass2020-09-251-0/+1
| | | | | | | Some Atom SoCs use SWSMISCI for SMI control. Add a Kconfig to select this. It is used on Apollo Lake. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: apl: Support writing the IntelGraphicsMem tableSimon Glass2020-09-251-0/+1
| | | | | | | This table is needed by the Linux graphics driver to handle graphics correctly. Write it to ACPI. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: acpi: Support external GNVS tablesSimon Glass2020-09-251-0/+1
| | | | | | | | | | | At present U-Boot puts a magic number in the ASL for the GNVS table and searches for it later. Add a Kconfig option to use a different approach, where the ASL files declare the table as an external symbol. U-Boot can then put it wherever it likes, without any magic numbers or searching. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add a config for the systemagent PCIEX regions sizeSimon Glass2020-09-251-0/+1
| | | | | | | Add a way to specify the required size for this region. This is used when generating ACPI tables. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: fsp: Replace e-mmc with emmc in devicetree bindingsWolfgang Wallner2020-09-211-3/+3
| | | | | | | | | | | | | | | | The term eMMC is used inconsistently within the FSP devicetree bindings (e-mmc and emmc), especially for "emmc-host-max-speed" documentation and code disagree. Change all eMMC instances within the FSP bindings to consistently use "emmc". The term "emmc" is already used a lot within U-Boot, while "e-mmc" is only used in the FSP bindings. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct one typo in the commit message] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* arch: x86: apl: Update FSP parametersBernhard Messerklinger2020-08-031-0/+23
| | | | | | | | Add missing parameters to support full configuration of the latest FSP MR6 release. Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: apl: fsp_bindings: Add support for u64 parametersBernhard Messerklinger2020-08-031-0/+28
| | | | | | | | Add FSP_UINT64 read support as preparation for FSP-M and FSP-S parameter update. Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* cpu: Convert the methods to use a const udevice *Simon Glass2020-07-251-1/+1
| | | | | | | These functions should not modify the device. Convert them to const so that callers don't need to cast if they have a const udevice *. Signed-off-by: Simon Glass <sjg@chromium.org>
* Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm"Tom Rini2020-07-241-1/+1
| | | | | | | | | | This reverts commit 5d3a21df6694ebd66d5c34c9d62a26edc7456fc7, reversing changes made to 56d37f1c564107e27d873181d838571b7d7860e7. Unfortunately this is causing CI failures: https://travis-ci.org/github/trini/u-boot/jobs/711313649 Signed-off-by: Tom Rini <trini@konsulko.com>
* cpu: Convert the methods to use a const udevice *Simon Glass2020-07-201-1/+1
| | | | | | | These functions should not modify the device. Convert them to const so that callers don't need to cast if they have a const udevice *. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit (git 2.34.1) at 2025-09-02 19:19:32 +0000