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* CONFIG_SPL_SYS_[DI]CACHE_OFF: addTrevor Woerner2019-05-182-4/+18
* CONFIG_SYS_[DI]CACHE_OFF: convert to KconfigTrevor Woerner2019-05-181-0/+12
* RISCV: image: Add booti supportAtish Patra2019-05-092-0/+56
* riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is ena...Rick Chen2019-05-092-0/+4
* riscv: Introduce CONFIG_XIP to support booting from flashRick Chen2019-05-096-0/+21
* dts: switch spi-flash to jedec, spi-nor compatibleNeil Armstrong2019-04-122-2/+2
* riscv: dts: fix CONFIG_DEFAULT_DEVICE_TREE failureRick Chen2019-04-081-0/+2
* riscv: dts: ae350 support SMPRick Chen2019-04-082-44/+118
* riscv: ax25: Andes specific cache shall only support in M-modeRick Chen2019-04-081-0/+1
* riscv: ax25: Add platform-specific Kconfig optionsRick Chen2019-04-081-0/+6
* riscv: Add a SYSCON driver for Andestech's PLMTRick Chen2019-04-085-0/+67
* riscv: Add a SYSCON driver for Andestech's PLICRick Chen2019-04-085-2/+127
* riscv: hang if relocation of secondary harts failsLukas Auer2019-04-081-1/+12
* riscv: do not rely on hart ID passed by previous boot stageLukas Auer2019-04-081-0/+4
* riscv: boot images passed to bootm on all hartsLukas Auer2019-04-081-1/+12
* riscv: add support for multi-hart systemsLukas Auer2019-04-085-2/+147
* riscv: save hart ID in register tp instead of s0Lukas Auer2019-04-081-2/+2
* riscv: delay initialization of caches and debug UARTLukas Auer2019-04-081-8/+8
* riscv: implement IPI platform functions using SBILukas Auer2019-04-083-0/+31
* riscv: import the supervisor binary interface header fileLukas Auer2019-04-081-0/+94
* riscv: add infrastructure for calling functions on other hartsLukas Auer2019-04-085-0/+197
* riscv: Enable CONFIG_SYS_BOOT_RAMDISK_HIGH for using initrdAnup Patel2019-02-271-0/+1
* riscv: Add SiFive FU540 board supportAnup Patel2019-02-271-0/+4
* riscv: generic: Ensure that U-Boot runs within 4GB for 64bit systemsAnup Patel2019-02-271-0/+20
* riscv: Add place-holder asm/arch/clk.h for driver compilationAnup Patel2019-02-271-0/+14
* riscv: Add asm/dma-mapping.h for DMA mappingsAnup Patel2019-02-271-0/+38
* riscv: Rename cpu/qemu to cpu/genericAnup Patel2019-02-275-2/+2
* riscv: qemu: define standalone load addressLukas Auer2019-01-151-1/+1
* riscv: remove RISC-V standalone linker scriptLukas Auer2019-01-151-1/+0
* riscv: use invalidate/flush_*cache_range functions in cache.cLukas Auer2019-01-151-2/+2
* riscv: move the AX25-specific implementation of flush_dcache_allLukas Auer2019-01-152-6/+26
* riscv: clarify error message on undefined exceptionsLukas Auer2019-01-151-1/+2
* riscv: bootm: Support booting VxWorksBin Meng2018-12-311-1/+7
* riscv: Remove ae350.dtsBin Meng2018-12-181-229/+0
* riscv: bootm: Change to use boot_hart from global dataBin Meng2018-12-181-1/+1
* riscv: Save boot hart id to the global dataBin Meng2018-12-183-0/+24
* riscv: Adjust the _exit_trap() position to come before handle_trap()Bin Meng2018-12-181-32/+30
* riscv: Return to previous privilege level after trap handlingBin Meng2018-12-181-8/+0
* riscv: Fix context restore before returning from trap handlerBin Meng2018-12-181-1/+1
* riscv: Move trap handler codes to mtrap.SBin Meng2018-12-183-90/+112
* riscv: Do some basic architecture level cpu initializationBin Meng2018-12-181-1/+26
* riscv: Add indirect stringification to csr_xxx opsBin Meng2018-12-181-7/+9
* riscv: Update supports_extension() to use desc from cpu driverBin Meng2018-12-181-0/+26
* riscv: Add exception codes for xcause registerBin Meng2018-12-181-0/+15
* riscv: Add CSR numbersBin Meng2018-12-181-0/+221
* riscv: Remove non-DM version of print_cpuinfo()Bin Meng2018-12-181-37/+0
* riscv: Probe cpus during bootBin Meng2018-12-182-0/+27
* riscv: Enlarge the default SYS_MALLOC_F_LENBin Meng2018-12-181-0/+3
* riscv: qemu: Add platform-specific Kconfig optionsBin Meng2018-12-182-0/+12
* riscv: Implement riscv_get_time() API using rdtime instructionAnup Patel2018-12-183-0/+47
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