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* riscv: dts: add SiFive Unmatched board supportGreen Wan2021-05-314-0/+1790
| | | | | | | Add dts files for SiFive Unmatched board. Signed-off-by: Green Wan <green.wan@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
* riscv: dts: add fu740 supportGreen Wan2021-05-312-0/+434
| | | | | | | | | | | Add dts support for fu740. The HiFive Unmatched support is based on fu740 cpu and drivers in following patch set. Signed-off-by: Green Wan <green.wan@sifive.com> [greentime.hu: set fu740 speed to 1.2GHz] Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
* riscv: ae350: Switch to use binman to generate u-boot.itbBin Meng2021-05-192-0/+4
| | | | | | | | | Use the new BINMAN_STANDALONE_FDT option for AE350 based SPL defconfigs, so that binman is now used to generate u-boot.itb. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com>
* riscv: qemu: Switch to use binman to generate u-boot.itbBin Meng2021-05-193-0/+17
| | | | | | | | | By utilizing the newly introduced BINMAN_STANDALONE_FDT option, along with a new dedicated device tree source file for the QEMU virt target used for binman only, we can now use binman to generate u-boot.itb. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* riscv: dts: Sort build targets in alphabetical orderBin Meng2021-05-191-1/+1
| | | | | | | | Sort the RISC-V DTS build targets by their Kconfig target names in alphabetical order. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* riscv: sifive: unleashed: Switch to use binman to generate u-boot.itbBin Meng2021-05-192-0/+71
| | | | | | | | | At present SiFive Unleashed board uses the Makefile to create the FIT, using USE_SPL_FIT_GENERATOR, which is deprecated as per the Makefile warning. Update to use binman instead. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* riscv: Don't reserve AI ram in k210 dtsSean Anderson2021-05-141-12/+0
| | | | | | | It is no longer necessary to disallow ai ram, since it is enabled by the sram driver. Signed-off-by: Sean Anderson <seanga2@gmail.com>
* riscv: k210: Use AI as the parent clock of aisram, not PLL1Sean Anderson2021-05-141-1/+1
| | | | | | | | Testing showed that disabling AI while leaving PLL1 enabled disabled the aisram. This suggests that AI is a more appropriate clock for that ram bank. Signed-off-by: Sean Anderson <seanga2@gmail.com>
* riscv: k210: Rename airam to aisramSean Anderson2021-05-141-2/+2
| | | | | | | | This is more consistent with the naming of other ram banks, and matches what Linux is doing. Reported-by: Damien Le Moal <Damien.LeMoal@wdc.com> Signed-off-by: Sean Anderson <seanga2@gmail.com>
* riscv: Enable some devices pre-relocationSean Anderson2021-05-141-0/+4
| | | | | | | These devices are necessary for the clock driver, which is required by the sram driver, to run pre-relocation. Signed-off-by: Sean Anderson <seanga2@gmail.com>
* riscv: dts: mpfs-icicle-kit: Drop 'clock-frequency' in the uart nodesBin Meng2021-04-081-4/+0
| | | | | | | | | | The uart nodes already provide <clocks> property for the driver to dynamically calculate the correct clock frequency. There is no need to keep the hard-coded <clock-frequency> property. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
* riscv: sifive: Rename fu540 board to unleashedBin Meng2021-04-081-1/+1
| | | | | | | | In preparation to add SiFive Unmatched board support, let's rename the existing fu540 board to unleashed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
* riscv: Add watchdog bindings for the k210Sean Anderson2021-04-081-1/+0
| | | | | | | This adds the necessary bindings. Most of them are already there. Signed-off-by: Sean Anderson <seanga2@gmail.com> Acked-by: Rick Chen <rick@andestech.com>
* riscv: k210: Enable QSPI for spi3Sean Anderson2021-02-251-0/+2
| | | | | | | | | This device has four IOs connected to the SPI flash. Add the appropriate bindings. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Leo Liang <ycliang@andestech.com>
* riscv: dts: Add device tree for Microchip Icicle KitPadmarao Begari2021-01-183-0/+436
| | | | | | | | Add device tree for Microchip PolarFire SoC Icicle Kit. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
* riscv: Add device tree bindings for SPISean Anderson2020-12-182-1/+47
| | | | | | | | | This patch adds bindings for the MMC slot and SPI flash on the Sipeed Maix Bit. Signed-off-by: Sean Anderson <seanga2@gmail.com> Acked-by: Rick Chen <rick@andestech.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* spi: dw: Add SoC-specific compatible stringsSean Anderson2020-12-181-5/+8
| | | | | | | | | | | | | | | | | This adds SoC-specific compatible strings to all users of the designware spi device. This will allow for the correct driver to be selected for each device. Where it is publicly documented, a compatible string for the specific device version has also been added. Devices without publicly-documented device versions include MSCC SoCs, and Arc Socs. All compatible strings except those for SoCFPGAs and some of the versioned strings have been taken from Linux. Since SSI_MAX_XFER_SIZE is determined at runtime, this is not strictly necessary. However, it is a good cleanup and brings things closer to Linux. Signed-off-by: Sean Anderson <seanga2@gmail.com> Tested-by Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* riscv: fu540: dts: Correct reg size of clint nodePragnesh Patel2020-10-261-1/+1
| | | | | | Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com>
* riscv: k210: Reduce DMA block sizeSean Anderson2020-10-261-2/+2
| | | | | | | | | | | Although the max DMA size supported by the hardware register is 22 bits (or 4M), the Linux driver for this device only supports transfers of up to 2M. On a device with 8M total memory, I don't think it will make too much of a difference. Reported-by: Damien Le Moal <Damien.LeMoal@wdc.com> Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
* riscv: add DT binding for BOOT button on Maix boardHeinrich Schuchardt2020-10-081-0/+11
| | | | | | | | | Add a device tree binding for the BOOT button on the Maix board. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Sean Anderson <seanga2@gmail.com> Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
* riscv: Add pinmux and gpio bindings for Kendryte K210Sean Anderson2020-10-082-0/+116
| | | | | | | | This patch adds the necessary device tree bindings. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Rick Chen <rick@andestech.com>
* riscv: Update SiFive device tree for new CLINT driverSean Anderson2020-09-302-2/+10
| | | | | | | | | We currently do this in a u-boot specific dts, but hopefully we can get these bindings added in Linux in the future. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@openfive.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
* riscv: Update Kendryte device tree for new CLINT driverSean Anderson2020-09-301-3/+4
| | | | | | | | | The interrupt controller property is removed from the clint binding because the clint is not an interrupt-controller. That is, no other devices have an interrupt which is controlled by the clint. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
* fu540: dtsi: add reset producer and consumer entriesSagar Shrikant Kadam2020-08-041-0/+12
| | | | | | | | | | | The resets to DDR and ethernet sub-system are connected to PRCI device reset control register, these reset signals are active low and are held low at power-up. Add these reset producer and consumer details needed by the reset driver. Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
* riscv: dts: hifive-unleashed-a00: Make memory node available to SPLBin Meng2020-07-241-0/+4
| | | | | | | | Make memory node available to SPL in prepration to updates to SiFive DDR RAM driver to read memory information from DT. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
* sifive: fu540: Add Booting from SPIJagan Teki2020-07-241-0/+12
| | | | | | | | Add booting from SPI for SiFive Unleashed board. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com>
* Merge branch 'next'Tom Rini2020-07-064-0/+646
|\ | | | | | | | | Merge all outstanding changes from the current next branch in now that we have released.
| * riscv: dts: hifive-unleashed-a00: add cpu aliasesSagar Shrikant Kadam2020-07-011-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add cpu aliases to U-Boot specific dtsi for hifive-unleashed. Without aliases we see that the CPU device sequence numbers are set randomly and the cpu list/detail command will show it as follows: => cpu list 1: cpu@1 rv64imafdc 2: cpu@2 rv64imafdc 3: cpu@3 rv64imafdc 0: cpu@4 rv64imafdc Seems like CPU probing with dm-model also relies on aliases as observed in case spi. The fu540-c000-u-boot.dtsi has cpu nodes and so adding corresponding aliases we can ensure that cpu devices are assigned proper sequence as follows: => cpu list 1: cpu@1 rv64imafdc 2: cpu@2 rv64imafdc 3: cpu@3 rv64imafdc 4: cpu@4 rv64imafdc Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
| * riscv: Add device tree for K210 and Sipeed Maix BitMSean Anderson2020-07-013-0/+642
| | | | | | | | | | | | | | | | | | Where possible, I have tried to find compatible drivers based on the layout of registers. However, many devices remain untested. All untested devices have been left disabled, but some tentative properties (such as compatible strings, and clocks, interrupts, and resets properties) have been added. Signed-off-by: Sean Anderson <seanga2@gmail.com>
* | riscv: sifive: fu540: enable all cache ways from U-Boot properPragnesh Patel2020-07-031-0/+4
| | | | | | | | | | | | | | | | Add L2 cache node to enable all cache ways from U-Boot proper. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* | riscv: fu540: dts: Correct reg size of otp and dmc nodesBin Meng2020-07-021-2/+2
| | | | | | | | | | Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
* | riscv: fu540: dts: Remove the unnecessary space in the cpu2_intc nodeBin Meng2020-07-021-1/+1
|/ | | | | Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
* riscv: sifive: fu540: add SPL configurationPragnesh Patel2020-06-041-0/+5
| | | | | | | | | | | | | | | Add a support for SPL which will boot from L2 LIM (0x0800_0000) and then SPL will boot U-Boot FIT image (OpenSBI FW_DYNAMIC + u-boot.bin) from MMC boot devices. SPL related code is leveraged from FSBL (https://github.com/sifive/freedom-u540-c000-bootloader.git) Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
* riscv: dts: sifive: Sync hifive-unleashed-a00 dts from linuxPragnesh Patel2020-06-042-1/+45
| | | | | | | | | | | | | | This sync has changes required to use GPIO in U-Boot and U-Boot SPL. Sync dts from linux v5.7-rc2 commit: "riscv: dts: Add GPIO reboot method to HiFive Unleashed DTS file" (sha1: 0a91330b2af9f71ceeeed483f92774182b58f6d9) Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
* riscv: sifive: dts: fu540: set ethernet clock ratePragnesh Patel2020-06-041-0/+5
| | | | | | | | | Set ethernet clock rate to 125 Mhz so that it will work with 1000Mbps, Earlier this is done by FSBL. With this change We can remove the ethernet clock rate code from FSBL. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* riscv: sifive: dts: fu540: add U-Boot dmc nodePragnesh Patel2020-06-041-0/+9
| | | | | | | | | | | Add dmc node to enable ddr driver. dmc is used to initialize the memory controller. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
* sifive: dts: fu540: Add DDR controller and phy register settingsPragnesh Patel2020-06-041-0/+1489
| | | | | | | | | | Add DDR controller and phy register settings, taken from fsbl (https://github.com/sifive/freedom-u540-c000-bootloader.git) Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
* riscv: sifive: dts: fu540: Add board -u-boot.dtsi filesPragnesh Patel2020-06-042-0/+76
| | | | | | | | | | | | | | | | | | Devicetree files in FU540 platform is synced from Linux, like other platforms does. Apart from these U-Boot in FU540 would also require some U-Boot specific node like clint. So, create board specific -u-boot.dtsi files. This would help of maintain U-Boot specific changes separately without touching Linux dts(i) files which indeed easy for syncing from Linux between releases. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
* riscv: sifive: fu540: Use OTP DM driver for serial environment variablePragnesh Patel2020-06-042-0/+16
| | | | | | | | | | Use the OTP DM driver to set the serial environment variable. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
* sifive: fu540: Enable spi-nor flash supportJagan Teki2020-04-301-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | HiFive Unleashed A00 support is25wp256 spi-nor flash, So enable the same and add test result log for future reference. Tested on SiFive FU540 board. Thanks to Sagar for various use cases and tests. [QUAD mode in dt with spi-tx-bus-width: <4>] pp opcode = 0x34 [QUAD MODE] read opcode = 0x6c [QUAD MODE] erase opcode = 0x21 SPI-NOR: 1. erase entire flash: Pass 2. write entire flash: Pass 3. read entire flash: Pass 4. cmp 32MiB read back data: Pass 5. MMC: Booted Linux and dtb from mmc [SPI MODE in dt with spi-tx-bus-width: <1>] pp opcode = 0x12 [SPI MODE] read opcode = 0xc [SPI MODE] erase opcode = 0x21 SPI-NOR: 1. erase entire flash: Pass 2. write entire flash: Pass 3. read entire flash: Pass 4. cmp 32MiB read back data: Pass 5. MMC: Booted Linux and dtb from mmc Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Sagar Kadam <sagar.kadam@sifive.com>
* riscv: dts: hifive-unleashed-a00: Add -u-boot.dtsiJagan Teki2020-04-301-0/+10
| | | | | | | | | | | | | | | | | | | Add U-Boot specific dts file for hifive-unleashed-a00, this would help to add u-boot specific properties and other node changes without touching the base dts(i) files which are easy to sync from Linux. Added spi2 alias for qspi2 as an initial u-boot specific property change. spi probing in current dm model is very much rely on aliases numbering. Even though the qspi2 can't come under any associated spi nor flash it would require to specify the same to make proper binding happen for other spi slaves. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Sagar Kadam <sagar.kadam@sifive.com>
* riscv: dts: Add #address-cells and #size-cells in nor nodeRick Chen2019-12-102-2/+6
| | | | | | | | | Those are required for cfi-flash driver to get correct address information. Also modify size description correctly. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Cc: Alan Kao <alankao@andestech.com>
* riscv: dts: Support four cores SMPRick Chen2019-12-102-6/+108
| | | | | | | | | Add CPU2 and CPU3 information in cpus node to support four cores SMP booting. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Cc: Alan Kao <alankao@andestech.com>
* riscv: dts: Add hifive-unleashed-a00 dts from LinuxJagan Teki2019-12-103-0/+348
| | | | | | | | | | | | | | | | | | Sync the hifive-unleashed-a00 dts from Linux with below commit details: commit <2993c9b04e616df0848b655d7202a707a70fc876> ("riscv: dts: HiFive Unleashed: add default chosen/stdout-path") Idea is to periodically sync the dts from Linux instead of tweaking internal changes one after another, so better not add any intermediate changes in between. This would help to maintain the dts files easy and meaningful since we are reusing device tree files from Linux. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
* riscv: dts: move out AE350 L2 node from cpus nodeRick Chen2019-09-032-12/+22
| | | | | | | | | | | | | | When L2 node exists inside cpus node, uclass_get_device can not parse L2 node successfully. So move it outside from cpus node. Also add tag-ram-ctl and data-ram-ctl attributes for v5l2 cache controller driver. This can adjust timing by requirement from dtb to improve performance. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dts: switch spi-flash to jedec, spi-nor compatibleNeil Armstrong2019-04-122-2/+2
| | | | | | | | | | | | | | | | | | | | There is no reason not to use the Linux "jedec,spi-nor" binding in U-Boot dts files. This compatible has been added in sf_probe, let use it. This patch switches to jedec,spi-nor when spi-flash is used in the DTS and DTSI files, and removed spi-flash when jedec,spi-nor is already present. The x86 dts are switched in a separate commit since it depends on a change in fdtdec. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Evgeniy Paltsev <paltsev@synopsys.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Patrick Delaunay <Patrick.delaunay@st.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* riscv: dts: fix CONFIG_DEFAULT_DEVICE_TREE failureRick Chen2019-04-081-0/+2
| | | | | | | | | | | | | | It occurs since commit 27cb7300ffda ("Ensure device tree DTS is compiled"). More details can refer to 89c2b5c02049aea746b1edee0b4e1d8519dec2f4 ARM: fix arch/arm/dts/Makefile Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
* riscv: dts: ae350 support SMPRick Chen2019-04-082-44/+118
| | | | | | | Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
* riscv: Remove ae350.dtsBin Meng2018-12-181-229/+0
| | | | | | | | This is not used by any board. Remove it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
* riscv: dts: Add ae350_32.dts for RV32IRick Chen2018-11-263-1/+458
| | | | | | | | Add ae350_32.dts for 32 bit. And also rename ae350.dts to ae350_64.dts for 64 bit. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
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