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* riscv: dts: add SiFive Unmatched board supportGreen Wan2021-05-314-0/+1790
* riscv: dts: add fu740 supportGreen Wan2021-05-312-0/+434
* riscv: ae350: Switch to use binman to generate u-boot.itbBin Meng2021-05-192-0/+4
* riscv: qemu: Switch to use binman to generate u-boot.itbBin Meng2021-05-193-0/+17
* riscv: dts: Sort build targets in alphabetical orderBin Meng2021-05-191-1/+1
* riscv: sifive: unleashed: Switch to use binman to generate u-boot.itbBin Meng2021-05-192-0/+71
* riscv: Don't reserve AI ram in k210 dtsSean Anderson2021-05-141-12/+0
* riscv: k210: Use AI as the parent clock of aisram, not PLL1Sean Anderson2021-05-141-1/+1
* riscv: k210: Rename airam to aisramSean Anderson2021-05-141-2/+2
* riscv: Enable some devices pre-relocationSean Anderson2021-05-141-0/+4
* riscv: dts: mpfs-icicle-kit: Drop 'clock-frequency' in the uart nodesBin Meng2021-04-081-4/+0
* riscv: sifive: Rename fu540 board to unleashedBin Meng2021-04-081-1/+1
* riscv: Add watchdog bindings for the k210Sean Anderson2021-04-081-1/+0
* riscv: k210: Enable QSPI for spi3Sean Anderson2021-02-251-0/+2
* riscv: dts: Add device tree for Microchip Icicle KitPadmarao Begari2021-01-183-0/+436
* riscv: Add device tree bindings for SPISean Anderson2020-12-182-1/+47
* spi: dw: Add SoC-specific compatible stringsSean Anderson2020-12-181-5/+8
* riscv: fu540: dts: Correct reg size of clint nodePragnesh Patel2020-10-261-1/+1
* riscv: k210: Reduce DMA block sizeSean Anderson2020-10-261-2/+2
* riscv: add DT binding for BOOT button on Maix boardHeinrich Schuchardt2020-10-081-0/+11
* riscv: Add pinmux and gpio bindings for Kendryte K210Sean Anderson2020-10-082-0/+116
* riscv: Update SiFive device tree for new CLINT driverSean Anderson2020-09-302-2/+10
* riscv: Update Kendryte device tree for new CLINT driverSean Anderson2020-09-301-3/+4
* fu540: dtsi: add reset producer and consumer entriesSagar Shrikant Kadam2020-08-041-0/+12
* riscv: dts: hifive-unleashed-a00: Make memory node available to SPLBin Meng2020-07-241-0/+4
* sifive: fu540: Add Booting from SPIJagan Teki2020-07-241-0/+12
* Merge branch 'next'Tom Rini2020-07-064-0/+646
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| * riscv: dts: hifive-unleashed-a00: add cpu aliasesSagar Shrikant Kadam2020-07-011-0/+4
| * riscv: Add device tree for K210 and Sipeed Maix BitMSean Anderson2020-07-013-0/+642
* | riscv: sifive: fu540: enable all cache ways from U-Boot properPragnesh Patel2020-07-031-0/+4
* | riscv: fu540: dts: Correct reg size of otp and dmc nodesBin Meng2020-07-021-2/+2
* | riscv: fu540: dts: Remove the unnecessary space in the cpu2_intc nodeBin Meng2020-07-021-1/+1
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* riscv: sifive: fu540: add SPL configurationPragnesh Patel2020-06-041-0/+5
* riscv: dts: sifive: Sync hifive-unleashed-a00 dts from linuxPragnesh Patel2020-06-042-1/+45
* riscv: sifive: dts: fu540: set ethernet clock ratePragnesh Patel2020-06-041-0/+5
* riscv: sifive: dts: fu540: add U-Boot dmc nodePragnesh Patel2020-06-041-0/+9
* sifive: dts: fu540: Add DDR controller and phy register settingsPragnesh Patel2020-06-041-0/+1489
* riscv: sifive: dts: fu540: Add board -u-boot.dtsi filesPragnesh Patel2020-06-042-0/+76
* riscv: sifive: fu540: Use OTP DM driver for serial environment variablePragnesh Patel2020-06-042-0/+16
* sifive: fu540: Enable spi-nor flash supportJagan Teki2020-04-301-0/+1
* riscv: dts: hifive-unleashed-a00: Add -u-boot.dtsiJagan Teki2020-04-301-0/+10
* riscv: dts: Add #address-cells and #size-cells in nor nodeRick Chen2019-12-102-2/+6
* riscv: dts: Support four cores SMPRick Chen2019-12-102-6/+108
* riscv: dts: Add hifive-unleashed-a00 dts from LinuxJagan Teki2019-12-103-0/+348
* riscv: dts: move out AE350 L2 node from cpus nodeRick Chen2019-09-032-12/+22
* dts: switch spi-flash to jedec, spi-nor compatibleNeil Armstrong2019-04-122-2/+2
* riscv: dts: fix CONFIG_DEFAULT_DEVICE_TREE failureRick Chen2019-04-081-0/+2
* riscv: dts: ae350 support SMPRick Chen2019-04-082-44/+118
* riscv: Remove ae350.dtsBin Meng2018-12-181-229/+0
* riscv: dts: Add ae350_32.dts for RV32IRick Chen2018-11-263-1/+458
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