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path: root/arch/riscv/cpu/start.S
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* riscv: Save boot hart id to the global dataBin Meng2018-12-181-0/+4
* riscv: Move trap handler codes to mtrap.SBin Meng2018-12-181-89/+0
* riscv: ax25-ae350: Pass dtb address to u-boot with a1 registerRick Chen2018-12-051-2/+0
* riscv: Add kconfig option to run U-Boot in S-modeAnup Patel2018-12-051-8/+15
* riscv: cache: Implement i/dcache [status, enable, disable]Rick Chen2018-11-261-0/+6
* riscv: save hart ID and device tree passed by prior boot stageLukas Auer2018-11-261-2/+10
* riscv: do not blindly modify the mstatus CSRLukas Auer2018-11-261-4/+4
* riscv: remove unused labels in start.SLukas Auer2018-11-261-9/+0
* Drop CONFIG_INIT_CRITICALBin Meng2018-11-261-13/+0
* riscv: align mtvec on a 4-byte boundaryLukas Auer2018-11-261-1/+1
* riscv: fix inconsistent use of spaces and tabs in start.SLukas Auer2018-11-261-161/+161
* riscv: Make start.S available for all targetsBin Meng2018-10-031-0/+292