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path: root/arch/riscv/cpu/fu540
Commit message (Expand)AuthorAgeFilesLines
* drivers: clk: add fu740 supportGreen Wan2021-05-311-1/+1
* riscv: Split SiFive CLINT support between SPL and U-Boot properBin Meng2021-05-171-1/+1
* Revert "riscv: cpu: fu740: clear feature disable CSR"Bin Meng2021-05-141-15/+0
* riscv: cpu: fu740: clear feature disable CSRGreen Wan2021-05-051-0/+15
* cpu: Rename SPL_CPU_SUPPORT to SPL_CPUSimon Glass2021-03-271-1/+1
* Merge branch '2021-02-02-drop-asm_global_data-when-unused'Tom Rini2021-02-152-0/+2
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| * common: Drop asm/global_data.h from common headerSimon Glass2021-02-022-0/+2
* | riscv: Adjust board_get_usable_ram_top() for 32-bitBin Meng2021-02-031-4/+3
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* riscv: sifive/fu540: kconfig: Enable support for Opencores I2C controllerPragnesh Patel2020-11-281-0/+2
* riscv: Rework riscv timer driver to only support S-modeSean Anderson2020-09-301-1/+1
* riscv: fu540: Use correct API to get L2 cache controller base addressBin Meng2020-08-251-1/+2
* riscv: sifive: fu540: redundant initializationHeinrich Schuchardt2020-08-141-1/+1
* riscv: sifive/fu540: kconfig: Move FU540 driver related options to the SoC levelBin Meng2020-08-141-0/+22
* riscv: sifive/fu540: spl: Rename soc_spl_init()Bin Meng2020-08-141-1/+1
* env: Enable SPI flash env for SiFive FU540Jagan Teki2020-07-241-0/+13
* riscv: sifive: fu540: enable all cache ways from U-Boot properPragnesh Patel2020-07-032-0/+54
* riscv: sifive: fu540: add SPL configurationPragnesh Patel2020-06-042-0/+27
* riscv: cpu: fu540: Add support for cpu fu540Pragnesh Patel2020-06-044-0/+82
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