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* riscv: cpu: fu740: clear feature disable CSRGreen Wan2021-05-311-0/+15
* drivers: clk: add fu740 supportGreen Wan2021-05-311-1/+1
* riscv: cpu: fu740: Add support for cpu fu740Green Wan2021-05-316-0/+187
* treewide: Convert macro and uses of __section(foo) to __section("foo")Marek Behún2021-05-241-2/+2
* riscv: qemu: Switch to use binman to generate u-boot.itbBin Meng2021-05-191-0/+1
* riscv: Split SiFive CLINT support between SPL and U-Boot properBin Meng2021-05-172-2/+3
* Revert "riscv: cpu: fu740: clear feature disable CSR"Bin Meng2021-05-141-15/+0
* riscv: cpu: fu740: clear feature disable CSRGreen Wan2021-05-051-0/+15
* riscv: cpu: Add callback to init each coreGreen Wan2021-05-052-0/+15
* cpu: Rename SPL_CPU_SUPPORT to SPL_CPUSimon Glass2021-03-273-3/+3
* Merge branch '2021-02-02-drop-asm_global_data-when-unused'Tom Rini2021-02-153-0/+3
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| * common: Drop asm/global_data.h from common headerSimon Glass2021-02-023-0/+3
* | riscv: Adjust board_get_usable_ram_top() for 32-bitBin Meng2021-02-032-8/+6
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* riscv: fix the wrong swap value registerBrad Kim2020-12-141-1/+1
* riscv: sifive/fu540: kconfig: Enable support for Opencores I2C controllerPragnesh Patel2020-11-281-0/+2
* timer: Add _TIMER suffix to Andes PLMT KconfigSean Anderson2020-10-261-1/+1
* riscv: Add some comments to start.SSean Anderson2020-09-301-2/+17
* riscv: Ensure gp is NULL or points to valid dataSean Anderson2020-09-301-3/+25
* riscv: Consolidate fences into AMOs for available_harts_lockSean Anderson2020-09-301-6/+3
* riscv: Clear pending IPIs on initializationSean Anderson2020-09-301-0/+20
* Revert "riscv: Clear pending interrupts before enabling IPIs"Sean Anderson2020-09-301-2/+0
* riscv: Rework riscv timer driver to only support S-modeSean Anderson2020-09-303-3/+3
* riscv: fu540: Use correct API to get L2 cache controller base addressBin Meng2020-08-251-1/+2
* riscv: sifive: fu540: redundant initializationHeinrich Schuchardt2020-08-141-1/+1
* riscv: sifive/fu540: kconfig: Move FU540 driver related options to the SoC levelBin Meng2020-08-141-0/+22
* riscv: sifive/fu540: spl: Rename soc_spl_init()Bin Meng2020-08-141-1/+1
* riscv: Fix linking error when building u-boot-spl with no SMP supportLeo Yu-Chi Liang2020-07-241-0/+2
* env: Enable SPI flash env for SiFive FU540Jagan Teki2020-07-241-0/+13
* riscv: Make SiFive HiFive Unleashed board boot againBin Meng2020-07-241-1/+1
* Merge branch 'next'Tom Rini2020-07-062-0/+17
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| * riscv: Add option to support RISC-V privileged spec 1.9Sean Anderson2020-07-011-0/+9
| * riscv: Clean up IPI initialization codeSean Anderson2020-07-011-0/+6
| * riscv: Clear pending interrupts before enabling IPIsSean Anderson2020-07-011-0/+2
* | riscv: sifive: fu540: enable all cache ways from U-Boot properPragnesh Patel2020-07-032-0/+54
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* riscv: sifive: fu540: add SPL configurationPragnesh Patel2020-06-042-0/+27
* riscv: cpu: fu540: Add support for cpu fu540Pragnesh Patel2020-06-044-0/+82
* riscv: Add _image_binary_end for SPLPragnesh Patel2020-06-041-0/+1
* common: Drop linux/bitops.h from common headerSimon Glass2020-05-181-0/+1
* common: Drop init.h from common headerSimon Glass2020-05-181-0/+1
* common: Drop net.h from common headerSimon Glass2020-05-182-0/+2
* riscv: Provide a mechanism to fix DT for reserved memoryAtish Patra2020-04-231-0/+1
* riscv: Introduce SPL_SMP Kconfig option for U-Boot SPLBin Meng2020-04-231-7/+7
* riscv: Merge unnecessary SMP ifdefs in start.SBin Meng2020-04-231-4/+0
* riscv: qemu: Remove the simple-bus driver for the SoC nodeBin Meng2020-04-231-14/+0
* riscv: ax25: cache: Remove SPL_RISCV_MMODE config checkPragnesh Patel2020-04-231-8/+8
* riscv: Remove unnecessary instructionSean Anderson2020-02-101-3/+2
* riscv: Add option to print registers on exceptionSean Anderson2020-02-101-1/+2
* riscv: Fix breakage caused by linker relaxationSean Anderson2020-02-101-1/+0
* common: Move relocate_code() to init.hSimon Glass2020-01-171-1/+1
* riscv: add option to wait for ack from secondary harts in smp functionsLukas Auer2019-12-101-0/+2
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