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* cpu: Rename SPL_CPU_SUPPORT to SPL_CPUSimon Glass2021-03-271-1/+1
* timer: Add _TIMER suffix to Andes PLMT KconfigSean Anderson2020-10-261-1/+1
* riscv: Rework riscv timer driver to only support S-modeSean Anderson2020-09-301-1/+1
* common: Drop net.h from common headerSimon Glass2020-05-181-0/+1
* riscv: ax25: cache: Remove SPL_RISCV_MMODE config checkPragnesh Patel2020-04-231-8/+8
* riscv: ax25: cache: Add SPL_RISCV_MMODE for SPLRick Chen2019-12-101-14/+46
* riscv: ax25: add SPL supportRick Chen2019-12-101-1/+3
* common: Move ARM cache operations out of common.hSimon Glass2019-12-021-0/+1
* common: Move some cache and MMU functions out of common.hSimon Glass2019-12-022-0/+2
* riscv: cache: use CCTL to flush d-cacheRick Chen2019-09-031-9/+13
* riscv: cache: Flush L2 cache before jump to linuxRick Chen2019-09-031-0/+17
* riscv: ax25: add imply v5l2 cache controllerRick Chen2019-09-031-0/+1
* riscv: add run mode configuration for SPLLukas Auer2019-08-261-3/+3
* CONFIG_SPL_SYS_[DI]CACHE_OFF: addTrevor Woerner2019-05-181-4/+4
* riscv: ax25: Andes specific cache shall only support in M-modeRick Chen2019-04-081-0/+1
* riscv: ax25: Add platform-specific Kconfig optionsRick Chen2019-04-081-0/+6
* riscv: move the AX25-specific implementation of flush_dcache_allLukas Auer2019-01-151-0/+22
* riscv: ax25: Hide the ax25-specific Kconfig optionBin Meng2018-12-182-11/+18
* riscv: cache: Implement i/dcache [status, enable, disable]Rick Chen2018-11-264-0/+107
* riscv: Move do_reset() to a common placeBin Meng2018-10-031-9/+0
* riscv: Make start.S available for all targetsBin Meng2018-10-032-294/+0
* riscv: Move the linker script to the CPU root directoryBin Meng2018-10-031-90/+0
* riscv: Include bss subsections in linker scriptAlexander Graf2018-08-201-1/+1
* efi_loader: Rename sections to allow for implicit dataAlexander Graf2018-07-251-10/+16
* riscv: cpu: nx25: Rename as ax25Rick Chen2018-05-294-0/+416
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