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* ARM: imx: ddr: Add deskew register programmingMarek Vasut2020-08-171-0/+9
| | | | | | | | | | | Fill is code for programming the DDR_PHY_CMD_DESKEW_CONx registers, which are optional, but can be used to fill in the byte lane delays. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* ARM: imx: ddr: Fill in missing DDRC ZQCTLx on i.MX7Marek Vasut2020-06-221-0/+1
| | | | | | | | | | | | | | | | The iMX7 defines further DDRC ZQCTLx registers, however those were thus far missing from the list of registers and not programmed. On systems with LPDDR2 or DDR3, those registers must be programmed with correct values, otherwise the DRAM may not work. However, existing systems which worked without programming these registers before are now setting those registers to 0, which is the default value, so no functional change there. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* ARM: imx: ddr: Add missing PHY resetMarek Vasut2020-06-081-3/+19
| | | | | | | | | | | | | | | | | The iMX7D RM 9.2.4.9.3 Power removal flow Table 9-11. Re-enabling power explicitly says both the DDR controller and the PHY must be reset in the correct sequence. Currently the code only resets the controller. This leads to a misbehavior where the system brings the DRAM up after reboot, but the DRAM is unstable. Add the missing reset. The easiest way to trigger this is by triggering WDT without having the WDT assert WDOG_B signal, i.e. mw.w 0x30280000 0x25 . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: mx7: fix potential overflow in imx_ddr_size()Marcel Ziswiler2018-10-091-0/+4
| | | | | | | | | The imx_ddr_size() function may overflow as it is possible to kind of over provision the DDR controller. Fix this by capping it to 2 GB which is the maximum allowed size as per reference manual. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
* SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini2018-05-071-2/+1
| | | | | | | | | | | | | | | | | | | | When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
* imx: mx7: DDR controller configuration for the i.MX7 architectureUri Mashiach2017-10-121-0/+201
The configuration files imximage.cfg are used for the DDR controller configuration. Add DDR configuration function to replace the DDR controller configuration in the imximage.cfg file. The function can be used for DDR size detection. Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>