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* ARM: imx8m: fix imx_eqos_txclk_set_rate() type mismatch for LTOMarek Behún2021-05-241-1/+1
| | | | | | | | | | | | | | When building imx8mp_evk_defconfig with LTO, the compiler complains about type mismatch of function imx_eqos_txclk_set_rate() in file drivers/net/dwc_eth_qos.c:845:12 which contains a weak definition of this function, vs file arch/arm/mach-imx/imx8m/clock_imx8mm.c which contains an implementation. Change the type of this function in the implementation to fix this. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* ARM: make gd a function call for LTO and set via set_gd()Marek Behún2021-05-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | On ARM, the gd pointer is stored in registers r9 / x18. For this the -ffixed-r9 / -ffixed-x18 flag is used when compiling, but using global register variables causes errors when building with LTO, and these errors are very difficult to overcome. Richard Biener says [1]: Note that global register vars shouldn't be used with LTO and if they are restricted to just a few compilation units the recommended fix is to build those CUs without -flto. We cannot do this for U-Boot since all CUs use -ffixed-reg flag. It seems that with LTO we could in fact store the gd pointer differently and gain performance or size benefit by allowing the compiler to use r9 / x18. But this would need more work. So for now, when building with LTO, go the clang way, and instead of declaring gd a global register variable, we make it a function call via macro. [1] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68384 Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Simon Glass <sjg@chromium.org>
* ARM:imx:imx8mq-cm: Add support for Ronetix iMX8MQ-CMIlko Iliev2021-05-021-5/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Supported peripherals: Ethernet, eMMC, Serial. U-Boot SPL 2021.04-00911-g5fa1e2ffeb-dirty (Apr 23 2021 - 09:11:14 +0200) Normal Boot Trying to boot from MMC2 U-Boot 2021.04-00911-g5fa1e2ffeb-dirty (Apr 23 2021 - 09:11:14 +0200) CPU: Freescale i.MX8MQ rev2.1 at 1000 MHz Reset cause: POR Model: Ronetix iMX8M-CM SoM DRAM: 1 GiB WDT: Started with servicing (60s timeout) MMC: FSL_SDHC: 0, FSL_SDHC: 1 Loading Environment from MMC... OK In: serial Out: serial Err: serial Net: Warning: ethernet@30be0000 (eth0) using random MAC address - 42:0d:e7:78:da:53 eth0: ethernet@30be0000 Hit any key to stop autoboot: 0 u-boot=> Signed-off-by: Ilko Iliev <iliev@ronetix.at>
* arm: imx8m: add support for Compulab iot-gate-imx8 (imx8mm-cl-iot-gate)Ying-Chun Liu (PaulLiu)2021-05-021-0/+8
| | | | | | | | | | | | | | | | Add initial support for Compulab iot-gate-imx8 board (imx8mm-cl-iot-gate). The initial support includes: - MMC - eMMC - I2C - FEC - Serial console Signed-off-by: Kirill Kapranov <kirill.kapranov@compulab.co.il> Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il> Signed-off-by: Valentin Raevsky <valentin@compulab.co.il> Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> Cc: Peter Robinson <pbrobinson@gmail.com>
* board: imx8mm: Add Engicam i.Core MX8M Mini C.TOUCH 2.0Jagan Teki2021-05-021-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose Carrier board. Genaral features: - Ethernet 10/100 - Wifi/BT - USB Type A/OTG - Audio Out - CAN - LVDS panel connector i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini from Engicam. i.Core MX8M Mini needs to mount on top of this Carrier board for creating complete i.Core MX8M Mini C.TOUCH 2.0 board. Linux dts commit details: commit <a142252061ff> ("arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini C.TOUCH 2.0") Add support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
* board: imx8mm: Add Engicam i.Core MX8M Mini EDIMM2.2 Starter KitJagan Teki2021-05-021-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Engicam EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive Evaluation Board. Genaral features: - LCD 7" C.Touch - microSD slot - Ethernet 1Gb - Wifi/BT - 2x LVDS Full HD interfaces - 3x USB 2.0 - 1x USB 3.0 - HDMI Out - Mini PCIe - MIPI CSI - 2x CAN - Audio Out i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini from Engicam. i.Core MX8M Mini needs to mount on top of this Evaluation board for creating complete i.Core MX8M Mini EDIMM2.2 Starter Kit. Linux dts commit details: commit <051c08eea682> ("arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini EDIMM2.2 Starter Kit") Add support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
* ARM: imx: Add OCRAM_S into iMX8M MMU tablesMarek Vasut2021-04-081-0/+7
| | | | | | | | | | The OCRAM_S is regular memory, just like the OCRAM, add it to the MMU tables so it can be used and cached. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* imx8mp-evk: switch to use binmanPeng Fan2021-04-081-0/+1
| | | | | | Use binman to pack images Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx8mn-evk: switch to use binmanPeng Fan2021-04-081-0/+1
| | | | | | Use binman to pack images. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx8mn-ddr4-evk: switch to use binmanPeng Fan2021-04-081-0/+1
| | | | | | Use binman to pack images Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx8mm_evk: switch to use binman to pack imagesPeng Fan2021-04-081-0/+1
| | | | | | Use binman to pack images Signed-off-by: Peng Fan <peng.fan@nxp.com>
* crypto: caam: Add CAAM support to i.MX8M platformsAymen Sghaier2021-04-081-0/+1
| | | | | | | This patch enable CAAM support for i.MX8M platforms. Signed-off-by: Aymen Sghaier <aymen.sghaier@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* iMX8M: Add support to enable CONFIG_IMX_HABYe Li2021-04-082-0/+15
| | | | | | | | | | | | | Add some SOC level codes and build configurations to use HAB lib for CONFIG_IMX_HAB (secure boot), like adding the SEC_CONFIG fuse, enable fuse driver, CAAM clock function, and add CAAM secure RAM to MMU table. The FSL_CAAM is temporally not enabled for iMX8M when CONFIG_IMX_HAB is set, because we don't need the CAAM driver for SPL. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* iMX8MQ: Recognize the B2 revisionYe Li2021-04-081-1/+10
| | | | | | | | | | | | i.MX8MQ B2 is using same value in OCOTP_READ_FUSE_DATA like B1, so we have to check the ROM verision to distinguish the revision. As we have checked the B1 rev for sticky bits work around in secure boot. So it won't apply on B2. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx8m: soc: update fuse pathPeng Fan2021-04-081-5/+10
| | | | | | | Update fuse path to disable modules correctly. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx8m: Update thermal and PMU kernel nodes for dual/single coresYe Li2021-04-081-0/+76
| | | | | | | | | | For dual core and single core iMX8M parts, the thermal node and PMU node in kernel DTB also needs update to remove the refers to deleted core nodes. Otherwise both driver will fail to work. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx8mn: Add support for 11x11 UltraLite part numberYe Li2021-04-081-12/+24
| | | | | | | | | | | | There are 3 part numbers for 11x11 i.MX8MNano with different core number configuration: UltraLite Quad/Dual/Solo Comparing with i.MX8MN Lite parts, they have MIPI DSI disabled. So checking the MIPI DSI disable fuse to recognize these parts. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx8mn: Add low drive mode support for DDR4/LPDDR4 EVKYe Li2021-04-081-0/+45
| | | | | | | | | Add dedicated defconfigs for iMX8MN low drive mode which set the VDD_SOC and VDD_DRAM to 0.8v, DDR at 1600MTS (800Mhz clock) and GPU at 200Mhz. Signed-off-by: Ye Li <ye.li@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx8mn: Add LPDDR4 EVK board supportPeng Fan2021-04-081-0/+6
| | | | | | | | Add support for iMX8MN LPDDR4 EVK board which uses 2GB LPDDR4 and PCA9450B PMIC. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* Merge tag 'v2021.04-rc4' into nextTom Rini2021-03-152-3/+23
|\ | | | | | | Prepare v2021.04-rc4
| * board: gateworks: imx8mm: Add Gateworks Venice board supportTim Harvey2021-03-031-0/+7
| | | | | | | | | | | | | | Add initial support for Gateworks Venice product family based on the i.MX 8M Mini SoC Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * ARM: imx: Do not hard-code MX8M MMU table DRAM entry offsetMarek Vasut2021-03-011-3/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | Instead of hard-coding the offset of DRAM entries in MMU table all over the code, auto-detect the offset. This removes error-prone code which would break e.g. in case the MMU table is modified. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
* | reset: Remove addr parameter from reset_cpu()Harald Seiler2021-03-021-1/+1
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Historically, the reset_cpu() function had an `addr` parameter which was meant to pass in an address of the reset vector location, where the CPU should reset to. This feature is no longer used anywhere in U-Boot as all reset_cpu() implementations now ignore the passed value. Generic code has been added which always calls reset_cpu() with `0` which means this feature can no longer be used easily anyway. Over time, many implementations seem to have "misunderstood" the existence of this parameter as a way to customize/parameterize the reset (e.g. COLD vs WARM resets). As this is not properly supported, the code will almost always not do what it is intended to (because all call-sites just call reset_cpu() with 0). To avoid confusion and to clean up the codebase from unused left-overs of the past, remove the `addr` parameter entirely. Code which intends to support different kinds of resets should be rewritten as a sysreset driver instead. This transformation was done with the following coccinelle patch: @@ expression argvalue; @@ - reset_cpu(argvalue) + reset_cpu() @@ identifier argname; type argtype; @@ - reset_cpu(argtype argname) + reset_cpu(void) { ... } Signed-off-by: Harald Seiler <hws@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* common: Drop asm/global_data.h from common headerSimon Glass2021-02-022-0/+2
| | | | | | | | | | | | Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* ARM: imx: add i.MX8MN lpddr4 image cfg fileMarek Vasut2021-01-231-0/+17
| | | | | | | | | Add cfg file for i.MX8MN LPDDR4 Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: Add support for i.MX8MN Beacon EmbeddedWorks devkit.Adam Ford2021-01-231-0/+7
| | | | | | | | | | | Beacon EmbeddedWorks is releasing a devkit based on the i.MX8M Nano SoC consisting of baseboard + SOM. The kit is based on the same design as the Beacon dev kit with the i.MX8M Mini. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
* board: phytec: imx8mp: Add PHYTEC phyCORE-i.MX8MP supportTeresa Remmet2021-01-231-0/+7
| | | | | | | | | | | | | | Add initial support PHYTEC phyCORE-i.MX8MP SOM. Supported features: - 2GB LPDDR4 RAM - eMMC - external SD - debug UART2 - watchdog Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Reviewed-by: Heiko Schocher <hs@denx.de>
* imx8m: lowlevel_init: tune alignmentPeng Fan2021-01-231-1/+1
| | | | | | The minimum alignment is 16 bytes, so use align 4 is enough. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx: imx8mn_ddr4_evk: Use CONFIG_TARGET_IMX8MN_DDR4_EVK for DDR4 EVK boardPeng Fan2021-01-231-1/+1
| | | | | | | use CONFIG_TARGET_IMX8MN_DDR4_EVK for DDR4 EVK board, we will use CONFIG_TARGET_IMX8MN_EVK for LPDDR4 EVK board. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx8m: fix cache setup for dynamic sdram sizeTim Harvey2020-12-061-0/+3
| | | | | | | | | | | the mem_map structure containing the size of SDRAM is used in various cache functions in cache_v8.c thus we need to update it with the sdram size the board is configured with as well. Without this the cache functions do not get setup properly and can hang in the case where a board reports more SDRAM than defined in PHYS_SDRAM_SIZE. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* board: phytec: imx8mm: Add PHYTEC phyCORE-i.MX8MM supportTeresa Remmet2020-11-011-0/+6
| | | | | | | | | | | | | | | Add support PHYTEC phyCORE-i.MX8MM SOM. Supported features: - 2GB LPDDR4 RAM - 1x 1Gbit Ethernet - eMMC - external SD - debug UART3 - watchdog - i2c eeprom Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
* imx8mp: Remove parts MIMX8ML7 and MIMX8ML5 supportPeng Fan2020-09-171-8/+4
| | | | | | | | Latest datasheet revE has removed MIMX8ML7D/5D/7C/5C parts, so update u-boot to remove decoding and support for those parts. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx8m: clock_imx8mm: add missed returnPeng Fan2020-09-171-0/+1
| | | | | | Add missed return Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx8m: soc: Remove unneeded spaceFabio Estevam2020-07-271-1/+1
| | | | | | | | | | | | | | | Checkpatch reports the following issue: ERROR: space prohibited before that ',' (ctx:WxW) #936: FILE: arch/arm/mach-imx/imx8m/soc.c:936: + 0, 0 , 0, 0, 0, 0, &res); Remove the unneeded space. ^ Reported-by: Tom Rini <trini@konsulko.com> Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
* treewide: convert bd_t to struct bd_info by coccinelleMasahiro Yamada2020-07-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Linux coding style guide (Documentation/process/coding-style.rst) clearly says: It's a **mistake** to use typedef for structures and pointers. Besides, using typedef for structures is annoying when you try to make headers self-contained. Let's say you have the following function declaration in a header: void foo(bd_t *bd); This is not self-contained since bd_t is not defined. To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h> #include <asm/u-boot.h> void foo(bd_t *bd); Then, the include direcective pulls in more bloat needlessly. If you use 'struct bd_info' instead, it is enough to put a forward declaration as follows: struct bd_info; void foo(struct bd_info *bd); Right, typedef'ing bd_t is a mistake. I used coccinelle to generate this commit. The semantic patch that makes this change is as follows: <smpl> @@ typedef bd_t; @@ -bd_t +struct bd_info </smpl> Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
* imx8m: implement armv8_el2_to_aarch32Peng Fan2020-07-141-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add iMX8M specific armv8_el2_to_aarch32 to let AArch64 mode U-Boot could boot aarch32 mode linux with FIT image as below: /dts-v1/; / { description = "Configuration to load ARM32 Linux"; images { kernel@1 { description = "ARM32 Linux kernel"; data = /incbin/("./Image"); type = "kernel"; arch = "arm"; os = "linux"; compression = "none"; load = <0x40008000>; entry = <0x40008000>; hash@1 { algo = "md5"; }; }; fdt@1 { description = "Flattened Device Tree blob"; data = /incbin/("./imx8mm-evk.dtb"); type = "flat_dt"; arch = "arm"; compression = "none"; load = <0x43000000>; hash@1 { algo = "md5"; }; }; }; configurations { default = "config@1"; config@1 { description = "fsl-imx8mm-evk"; kernel = "kernel@1"; fdt = "fdt@1"; }; }; }; Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx8m: Refactor the OPTEE memory removalPeng Fan2020-07-141-7/+115
| | | | | | | | | | | | | | | Current codes assume the OPTEE address is at the end of first DRAM bank. Adjust the process to allow OPTEE in the middle of first bank. When OPTEE memory is removed from first bank, it may split the first bank to two banks, adjust the MMU table for the split case, Since the default CONFIG_NR_DRAM_BANKS is 4, it is enough, just enlarge i.MX8MP evk to default to avoid issue. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com> Tested-by: Silvano di Ninno <silvano.dininno@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx8m: disable nodes before kernel/mfgtool boot for fused partPeng Fan2020-07-141-0/+333
| | | | | | | | | To fused part, we need to disable nodes of dtb to let kernel boot. To mfgtool, USB issue when using super-speed for mfgtool, temporally work around the problem to use high-speed only. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx8mn/imx8mp: override env_get_offset and env_get_locationYe Li2020-07-141-0/+59
| | | | | | | | | | To use one defconfig for all boot device, we have to runtime set env offset and return env medium according to the boot device. This patch overrides the env_get_offset and env_get_location to implement the feature. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx8m: power down fused coresPeng Fan2020-07-141-0/+19
| | | | | | | For non-Quad SoCs, the fused cpu cores could be powered down in SPL to save power. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx8mp: Add fused parts supportYe Li2020-07-141-1/+33
| | | | | | | | | | | | | | | | | | | iMX8MP has 6 fused parts in each qualification tier, with core, VPU, ISP, NPU or DSP fused respectively. The configuration tables for enabled modules: MIMX8ML8DVNLZAA Quad Core, VPU, NPU, ISP, DSP MIMX8ML7DVNLZAA Quad Core, NPU, ISP MIMX8ML6DVNLZAA Quad Core, VPU, ISP MIMX8ML5DVNLZAA Quad Core, VPU MIMX8ML4DVNLZAA Quad Lite MIMX8ML3DVNLZAA Dual Core, VPU, NPU, ISP, DSP Add the support in U-Boot Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx8m: workaround ROM serrorPeng Fan2020-07-141-0/+38
| | | | | | | | | | | | | | | | | | | ROM SError happens on two cases: 1. ERR050342, on iMX8MQ HDCP enabled parts ROM writes to GPV1 register, but when ROM patch lock is fused, this write will cause SError. 2. ERR050350, on iMX8MQ/MM/MN, when the field return fuse is burned, HAB is field return mode, but the last 4K of ROM is still protected and cause SError. Since ROM mask SError until ATF unmask it, so then ATF always meets the exception. This patch works around the issue in SPL by enabling SPL Exception vectors table and the SError exception, take the exception to eret immediately to clear the SError. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx8m: add eqos clkPeng Fan2020-07-141-0/+90
| | | | | | | | | Add imx_eqos_txclk_set_rate/imx_get_eqos_csr_clk to override the weak function in driver Add set_clk_eqos to configure eQoS clk Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx8m: add sdhc/nand/ecspi clk apiPeng Fan2020-07-141-0/+66
| | | | | | | | | Current DM CLK is a bit complicated, for simplity, let DM clk only support enable/disable/get_rate. For the expected rate settings, we use non-DM clk to do that. Then we could have simple DM clk for i.MX and could also share between SPL/U-Boot proper. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx8m: configure NoC clkPeng Fan2020-07-141-0/+13
| | | | | | Configure NoC clk for better system performance Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx8m: configure arm clk sources from PLLPeng Fan2020-07-141-1/+129
| | | | | | | A53 CCM root max support 1GHz, to support high freq, we need to switch ARM clk sources from ARM PLL directly. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx8m: soc: use arm_smccc_smcPeng Fan2020-07-141-2/+5
| | | | | | Use arm_smccc_smc to replace call_imx_sip Signed-off-by: Peng Fan <peng.fan@nxp.com>
* common: Drop linux/bitops.h from common headerSimon Glass2020-05-182-0/+2
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop linux/delay.h from common headerSimon Glass2020-05-182-0/+2
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop log.h from common headerSimon Glass2020-05-181-0/+1
| | | | | | Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit (git 2.34.1) at 2025-09-02 04:34:31 +0000