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| author | Samuel Holland <samuel@sholland.org> | 2021-02-07 23:57:20 -0600 |
|---|---|---|
| committer | Andre Przywara <andre.przywara@arm.com> | 2021-04-16 01:12:59 +0100 |
| commit | fa7eabf650ae8ad904b1258f1dd6bcc02922bafe (patch) | |
| tree | ec7b703e3d5eb545ca71527149ecbe7f7b131d2c /drivers/clk/sunxi | |
| parent | 9078b67f3c968cbc3142432decc93a51780b4642 (diff) | |
| download | u-boot-fa7eabf650ae8ad904b1258f1dd6bcc02922bafe.tar.gz u-boot-fa7eabf650ae8ad904b1258f1dd6bcc02922bafe.tar.xz u-boot-fa7eabf650ae8ad904b1258f1dd6bcc02922bafe.zip | |
clk: sunxi: h6: Add XHCI clocks
The XHCI controller has its own clock and reset. Add them.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Diffstat (limited to 'drivers/clk/sunxi')
| -rw-r--r-- | drivers/clk/sunxi/clk_h6.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/sunxi/clk_h6.c b/drivers/clk/sunxi/clk_h6.c index ac8656fe89..df93d96b3b 100644 --- a/drivers/clk/sunxi/clk_h6.c +++ b/drivers/clk/sunxi/clk_h6.c @@ -43,6 +43,7 @@ static struct ccu_clk_gate h6_gates[] = { [CLK_BUS_OHCI0] = GATE(0xa8c, BIT(0)), [CLK_BUS_OHCI3] = GATE(0xa8c, BIT(3)), [CLK_BUS_EHCI0] = GATE(0xa8c, BIT(4)), + [CLK_BUS_XHCI] = GATE(0xa8c, BIT(5)), [CLK_BUS_EHCI3] = GATE(0xa8c, BIT(7)), [CLK_BUS_OTG] = GATE(0xa8c, BIT(8)), }; @@ -71,6 +72,7 @@ static struct ccu_reset h6_resets[] = { [RST_BUS_OHCI0] = RESET(0xa8c, BIT(16)), [RST_BUS_OHCI3] = RESET(0xa8c, BIT(19)), [RST_BUS_EHCI0] = RESET(0xa8c, BIT(20)), + [RST_BUS_XHCI] = RESET(0xa8c, BIT(21)), [RST_BUS_EHCI3] = RESET(0xa8c, BIT(23)), [RST_BUS_OTG] = RESET(0xa8c, BIT(24)), }; |