clk: sunxi: Add Allwinner H3/H5 CLK driver

Add initial clock driver for Allwinner H3/H5.

- Implement USB bus and USB clocks via ccu_clk_gate table for
  H3/H5, so it can accessed in common clk enable and disable
  functions from clk_sunxi.c
- Implement USB bus and USB resets via ccu_reset table for
  H3/H5, so it can accessed in common reset deassert and assert
  functions from reset-sunxi.c

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>

3 files changed, 87 insertions, 0 deletions

diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig
index 041d711e58..c3713bbac2 100644
--- a/drivers/clk/sunxi/Kconfig
+++ b/drivers/clk/sunxi/Kconfig
@@ -9,6 +9,13 @@ config CLK_SUNXI
 
 if CLK_SUNXI
 
+config CLK_SUN8I_H3
+	bool "Clock driver for Allwinner H3/H5"
+	default MACH_SUNXI_H3_H5
+	help
+	  This enables common clock driver support for platforms based
+	  on Allwinner H3/H5 SoC.
+
 config CLK_SUN50I_A64
 	bool "Clock driver for Allwinner A64"
 	default MACH_SUN50I
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index fb20d28333..dec49f27a1 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -6,4 +6,5 @@
 
 obj-$(CONFIG_CLK_SUNXI) += clk_sunxi.o
 
+obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o
 obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o
diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c
new file mode 100644
index 0000000000..9ee5c33b87
--- /dev/null
+++ b/drivers/clk/sunxi/clk_h3.c
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2018 Amarula Solutions.
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/arch/ccu.h>
+#include <dt-bindings/clock/sun8i-h3-ccu.h>
+#include <dt-bindings/reset/sun8i-h3-ccu.h>
+
+static struct ccu_clk_gate h3_gates[] = {
+	[CLK_BUS_OTG]		= GATE(0x060, BIT(23)),
+	[CLK_BUS_EHCI0]		= GATE(0x060, BIT(24)),
+	[CLK_BUS_EHCI1]		= GATE(0x060, BIT(25)),
+	[CLK_BUS_EHCI2]		= GATE(0x060, BIT(26)),
+	[CLK_BUS_EHCI3]		= GATE(0x060, BIT(27)),
+	[CLK_BUS_OHCI0]		= GATE(0x060, BIT(28)),
+	[CLK_BUS_OHCI1]		= GATE(0x060, BIT(29)),
+	[CLK_BUS_OHCI2]		= GATE(0x060, BIT(30)),
+	[CLK_BUS_OHCI3]		= GATE(0x060, BIT(31)),
+
+	[CLK_USB_PHY0]		= GATE(0x0cc, BIT(8)),
+	[CLK_USB_PHY1]		= GATE(0x0cc, BIT(9)),
+	[CLK_USB_PHY2]		= GATE(0x0cc, BIT(10)),
+	[CLK_USB_PHY3]		= GATE(0x0cc, BIT(11)),
+	[CLK_USB_OHCI0]		= GATE(0x0cc, BIT(16)),
+	[CLK_USB_OHCI1]		= GATE(0x0cc, BIT(17)),
+	[CLK_USB_OHCI2]		= GATE(0x0cc, BIT(18)),
+	[CLK_USB_OHCI3]		= GATE(0x0cc, BIT(19)),
+};
+
+static struct ccu_reset h3_resets[] = {
+	[RST_USB_PHY0]		= RESET(0x0cc, BIT(0)),
+	[RST_USB_PHY1]		= RESET(0x0cc, BIT(1)),
+	[RST_USB_PHY2]		= RESET(0x0cc, BIT(2)),
+	[RST_USB_PHY3]		= RESET(0x0cc, BIT(3)),
+
+	[RST_BUS_OTG]		= RESET(0x2c0, BIT(23)),
+	[RST_BUS_EHCI0]		= RESET(0x2c0, BIT(24)),
+	[RST_BUS_EHCI1]		= RESET(0x2c0, BIT(25)),
+	[RST_BUS_EHCI2]		= RESET(0x2c0, BIT(26)),
+	[RST_BUS_EHCI3]		= RESET(0x2c0, BIT(27)),
+	[RST_BUS_OHCI0]		= RESET(0x2c0, BIT(28)),
+	[RST_BUS_OHCI1]		= RESET(0x2c0, BIT(29)),
+	[RST_BUS_OHCI2]		= RESET(0x2c0, BIT(30)),
+	[RST_BUS_OHCI3]		= RESET(0x2c0, BIT(31)),
+};
+
+static const struct ccu_desc h3_ccu_desc = {
+	.gates = h3_gates,
+	.resets = h3_resets,
+};
+
+static int h3_clk_bind(struct udevice *dev)
+{
+	return sunxi_reset_bind(dev, ARRAY_SIZE(h3_resets));
+}
+
+static const struct udevice_id h3_ccu_ids[] = {
+	{ .compatible = "allwinner,sun8i-h3-ccu",
+	  .data = (ulong)&h3_ccu_desc },
+	{ .compatible = "allwinner,sun50i-h5-ccu",
+	  .data = (ulong)&h3_ccu_desc },
+	{ }
+};
+
+U_BOOT_DRIVER(clk_sun8i_h3) = {
+	.name		= "sun8i_h3_ccu",
+	.id		= UCLASS_CLK,
+	.of_match	= h3_ccu_ids,
+	.priv_auto_alloc_size	= sizeof(struct ccu_priv),
+	.ops		= &sunxi_clk_ops,
+	.probe		= sunxi_clk_probe,
+	.bind		= h3_clk_bind,
+};