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| author | Marek Vasut <marek.vasut+renesas@gmail.com> | 2018-01-11 16:28:31 +0100 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2018-02-16 16:43:09 +0100 |
| commit | fd5577ce26e18932bb5d4db02591625e46f2e9cc (patch) | |
| tree | 8b5c1743c9af8d619e9709e5907a88cb03302990 /drivers/clk/renesas/clk-rcar-gen3.c | |
| parent | 32fe36574ea5e6ea55313e16547b98a984af7767 (diff) | |
| download | u-boot-fd5577ce26e18932bb5d4db02591625e46f2e9cc.tar.gz u-boot-fd5577ce26e18932bb5d4db02591625e46f2e9cc.tar.xz u-boot-fd5577ce26e18932bb5d4db02591625e46f2e9cc.zip | |
clk: rmobile: Assure SD-IF clock are configured correctly
The SD driver calls clk_set_rate() before clk_enable(), yet clk_set_rate()
implementation in the clock driver does not set the SD-IF divider. Fix it.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Diffstat (limited to 'drivers/clk/renesas/clk-rcar-gen3.c')
| -rw-r--r-- | drivers/clk/renesas/clk-rcar-gen3.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c index 0c394a8a71..1be3fe7136 100644 --- a/drivers/clk/renesas/clk-rcar-gen3.c +++ b/drivers/clk/renesas/clk-rcar-gen3.c @@ -288,6 +288,8 @@ static ulong gen3_clk_get_rate(struct clk *clk) static ulong gen3_clk_set_rate(struct clk *clk, ulong rate) { + /* Force correct SD-IF divider configuration if applicable */ + gen3_clk_setup_sdif_div(clk); return gen3_clk_get_rate(clk); } |