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| author | Philipp Tomsich <philipp.tomsich@theobroma-systems.com> | 2017-12-02 00:14:55 +0100 |
|---|---|---|
| committer | Philipp Tomsich <philipp.tomsich@theobroma-systems.com> | 2017-12-02 00:27:31 +0100 |
| commit | cd401abcd532c59cdaaf6ffeed762386c1813e58 (patch) | |
| tree | c2ab05cdd59390fa3f7fccecdbdb8036a1472ce3 /arch | |
| parent | 5f104178bf713615dc404fdfcf0fb53d89c66a07 (diff) | |
| download | u-boot-cd401abcd532c59cdaaf6ffeed762386c1813e58.tar.gz u-boot-cd401abcd532c59cdaaf6ffeed762386c1813e58.tar.xz u-boot-cd401abcd532c59cdaaf6ffeed762386c1813e58.zip | |
rockchip: clk: rk3128: fix NANDC_PLL_SEL_MASK
The PLL selector field for NANDC is only 2 bits wide.
This fixes an 'int-overflow on shift' warning.
Fixes: 9246d9e ("rockchip: rk3128: add clock driver")
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/include/asm/arch-rockchip/cru_rk3128.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3128.h b/arch/arm/include/asm/arch-rockchip/cru_rk3128.h index cc317dc405..3d8317ed91 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3128.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3128.h @@ -136,7 +136,7 @@ enum { /* CRU_CLK_SEL2_CON */ NANDC_PLL_SEL_SHIFT = 14, - NANDC_PLL_SEL_MASK = 7 << NANDC_PLL_SEL_SHIFT, + NANDC_PLL_SEL_MASK = 3 << NANDC_PLL_SEL_SHIFT, NANDC_PLL_SEL_CPLL = 0, NANDC_PLL_SEL_GPLL, NANDC_CLK_DIV_SHIFT = 8, |