From cd401abcd532c59cdaaf6ffeed762386c1813e58 Mon Sep 17 00:00:00 2001 From: Philipp Tomsich Date: Sat, 2 Dec 2017 00:14:55 +0100 Subject: rockchip: clk: rk3128: fix NANDC_PLL_SEL_MASK The PLL selector field for NANDC is only 2 bits wide. This fixes an 'int-overflow on shift' warning. Fixes: 9246d9e ("rockchip: rk3128: add clock driver") Signed-off-by: Philipp Tomsich --- arch/arm/include/asm/arch-rockchip/cru_rk3128.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3128.h b/arch/arm/include/asm/arch-rockchip/cru_rk3128.h index cc317dc405..3d8317ed91 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3128.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3128.h @@ -136,7 +136,7 @@ enum { /* CRU_CLK_SEL2_CON */ NANDC_PLL_SEL_SHIFT = 14, - NANDC_PLL_SEL_MASK = 7 << NANDC_PLL_SEL_SHIFT, + NANDC_PLL_SEL_MASK = 3 << NANDC_PLL_SEL_SHIFT, NANDC_PLL_SEL_CPLL = 0, NANDC_PLL_SEL_GPLL, NANDC_CLK_DIV_SHIFT = 8, -- cgit