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| author | Sean Anderson <seanga2@gmail.com> | 2020-06-24 06:41:19 -0400 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2020-07-01 15:01:22 +0800 |
| commit | b8bc120927a75ccbdd3a242555933dc644391bc8 (patch) | |
| tree | c45afd3e5baf6fe2c64ce1a35125eee0b240d313 /arch/riscv/Kconfig | |
| parent | 40686c394e533fec765fe237936e353c84e73fff (diff) | |
| download | u-boot-b8bc120927a75ccbdd3a242555933dc644391bc8.tar.gz u-boot-b8bc120927a75ccbdd3a242555933dc644391bc8.tar.xz u-boot-b8bc120927a75ccbdd3a242555933dc644391bc8.zip | |
riscv: Add option to support RISC-V privileged spec 1.9
Some older processors (notably the Kendryte K210) use an older version of
the RISC-V privileged specification. The primary changes between the old
and new are in virtual memory, and in the merging of three separate counter
enable CSRs. Using the new CSR on an old processor causes an illegal
instruction exception. This patch adds an option to use the old CSRs
instead of the new one.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/riscv/Kconfig')
| -rw-r--r-- | arch/riscv/Kconfig | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index d9854f5283..ec5631c640 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -269,6 +269,16 @@ config XIP config SHOW_REGS bool "Show registers on unhandled exception" +config RISCV_PRIV_1_9 + bool "Use version 1.9 of the RISC-V priviledged specification" + help + Older versions of the RISC-V priviledged specification had + separate counter enable CSRs for each privilege mode. Writing + to the unified mcounteren CSR on a processor implementing the + old specification will result in an illegal instruction + exception. In addition to counter CSR changes, the way virtual + memory is configured was also changed. + config STACK_SIZE_SHIFT int default 14 |