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| author | Rick Chen <rick@andestech.com> | 2019-04-02 15:56:40 +0800 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2019-04-08 09:45:08 +0800 |
| commit | a1f24875c346a1bf8940b793a27364631d9aabf7 (patch) | |
| tree | d3117a234e71e0518a3f0589b4d21db3d00ca696 /arch/riscv/Kconfig | |
| parent | 0d389468e2144f3ba3bdbc566c05c0c05dc14fc6 (diff) | |
| download | u-boot-a1f24875c346a1bf8940b793a27364631d9aabf7.tar.gz u-boot-a1f24875c346a1bf8940b793a27364631d9aabf7.tar.xz u-boot-a1f24875c346a1bf8940b793a27364631d9aabf7.zip | |
riscv: Add a SYSCON driver for Andestech's PLMT
The platform-Level Machine Timer (PLMT) block
holds memory-mapped mtime register associated
with timer tick.
This driver implements the riscv_get_time() which
is required by the generic RISC-V timer driver.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Diffstat (limited to 'arch/riscv/Kconfig')
| -rw-r--r-- | arch/riscv/Kconfig | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 511768befc..ae8ff7b765 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -118,6 +118,15 @@ config ANDES_PLIC The Andes PLIC block holds memory-mapped claim and pending registers associated with software interrupt. +config ANDES_PLMT + bool + depends on RISCV_MMODE + select REGMAP + select SYSCON + help + The Andes PLMT block holds memory-mapped mtime register + associated with timer tick. + config RISCV_RDTIME bool default y if RISCV_SMODE |