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| author | Stefan Roese <sr@denx.de> | 2016-01-07 14:03:11 +0100 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2016-01-14 14:08:59 +0100 |
| commit | d35831f6fedbdfb0ce49814a225e854e5fa83c99 (patch) | |
| tree | 60f9d8293e9dc5a7461d89836738a46a0cbc4c7a /arch/arm/mach-mvebu/cpu.c | |
| parent | b7ca2501892887583de7d921e8dc332fc8d67f2f (diff) | |
| download | u-boot-d35831f6fedbdfb0ce49814a225e854e5fa83c99.tar.gz u-boot-d35831f6fedbdfb0ce49814a225e854e5fa83c99.tar.xz u-boot-d35831f6fedbdfb0ce49814a225e854e5fa83c99.zip | |
arm: mvebu: Move SAR register defines into header
This is preparation for the runtime bootmode detection in spl.c.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <dirk.eibach@gdsys.cc>
Cc: Phil Sutter <phil@nwl.cc>
Cc: Kevin Smith <kevin.smith@elecsyscorp.com>
Diffstat (limited to 'arch/arm/mach-mvebu/cpu.c')
| -rw-r--r-- | arch/arm/mach-mvebu/cpu.c | 19 |
1 files changed, 3 insertions, 16 deletions
diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 6ea558c69f..bc6a9e546c 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de> + * Copyright (C) 2014-2016 Stefan Roese <sr@denx.de> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -62,11 +62,7 @@ int mvebu_soc_family(void) #if defined(CONFIG_DISPLAY_CPUINFO) #if defined(CONFIG_ARMADA_38X) -/* SAR values for Armada 38x */ -#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18600)) -#define SAR_CPU_FREQ_OFFS 10 -#define SAR_CPU_FREQ_MASK (0x1f << SAR_CPU_FREQ_OFFS) - +/* SAR frequency values for Armada 38x */ struct sar_freq_modes sar_freq_tab[] = { { 0x0, 0x0, 666, 333, 333 }, { 0x2, 0x0, 800, 400, 400 }, @@ -77,16 +73,7 @@ struct sar_freq_modes sar_freq_tab[] = { { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */ }; #else -/* SAR values for Armada XP */ -#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230)) -#define CONFIG_SAR2_REG (MVEBU_REGISTER(0x18234)) -#define SAR_CPU_FREQ_OFFS 21 -#define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS) -#define SAR_FFC_FREQ_OFFS 24 -#define SAR_FFC_FREQ_MASK (0xf << SAR_FFC_FREQ_OFFS) -#define SAR2_CPU_FREQ_OFFS 20 -#define SAR2_CPU_FREQ_MASK (0x1 << SAR2_CPU_FREQ_OFFS) - +/* SAR frequency values for Armada XP */ struct sar_freq_modes sar_freq_tab[] = { { 0xa, 0x5, 800, 400, 400 }, { 0x1, 0x5, 1066, 533, 533 }, |