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authorYe Li <ye.li@nxp.com>2016-01-26 22:01:58 +0800
committerStefano Babic <sbabic@denx.de>2016-02-02 21:25:50 +0100
commit23e2da27d3de94117c099a511c7bfec759ede623 (patch)
tree90207b89532bcfcf7f216c7e3224d0b50d52018f
parent9655ebdd50c42f24179d738e4e6230c048f41de1 (diff)
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imx: mx6ul/sx: Fix issue in LCDIF clock dividers calculation
The checking with max frequency supported is not correct, because the temp is calculated by max pre and post dividers. We can decrease any divider to meet the max frequency limitation. Actually, the calculation below the codes is doing this way to find best pre and post dividers. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
-rw-r--r--arch/arm/cpu/armv7/mx6/clock.c4
1 files changed, 0 insertions, 4 deletions
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 007204dd4d..88380a6cd9 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -638,10 +638,6 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
}
temp = freq * max_pred * max_postd;
- if (temp > max) {
- puts("Please decrease freq, too large!\n");
- return;
- }
if (temp < min) {
/*
* Register: PLL_VIDEO