diff options
24 files changed, 2340 insertions, 4 deletions
diff --git a/arm64-tegra-Add-NVIDIA-Jetson-Nano-Developer-Kit-support.patch b/arm64-tegra-Add-NVIDIA-Jetson-Nano-Developer-Kit-support.patch new file mode 100644 index 000000000..a1a67acb7 --- /dev/null +++ b/arm64-tegra-Add-NVIDIA-Jetson-Nano-Developer-Kit-support.patch @@ -0,0 +1,2072 @@ +From patchwork Mon Mar 18 23:23:13 2019 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Thierry Reding <thierry.reding@gmail.com> +X-Patchwork-Id: 10858639 +Return-Path: + <linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org> +Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org + [172.30.200.125]) + by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A67F4139A + for <patchwork-linux-arm@patchwork.kernel.org>; + Mon, 18 Mar 2019 23:23:33 +0000 (UTC) +Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) + by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6F8DE29533 + for <patchwork-linux-arm@patchwork.kernel.org>; + Mon, 18 Mar 2019 23:23:33 +0000 (UTC) +Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) + id 633B329535; Mon, 18 Mar 2019 23:23:33 +0000 (UTC) +X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on + pdx-wl-mail.web.codeaurora.org +X-Spam-Level: +X-Spam-Status: No, + score=-5.2 required=2.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, + DKIM_SIGNED,DKIM_VALID,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED + autolearn=ham version=3.3.1 +Received: from bombadil.infradead.org (bombadil.infradead.org + [198.137.202.133]) + (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A839F29534 + for <patchwork-linux-arm@patchwork.kernel.org>; + Mon, 18 Mar 2019 23:23:30 +0000 (UTC) +DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; + d=lists.infradead.org; s=bombadil.20170209; h=Sender: + Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: + List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:To + :From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: + Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: + List-Owner; bh=2sU+x4hpA091D/jLGC2R38K/qJyHoHy9wmqJHJ4ewwg=; b=s0ieDGUxGdSDNa + vX5s18fXiTjoB7P9zv0GlxWzXQCJqQnxdX57USnUmcJMrg1Gzh0oO6+LbDlASCJSEu4t4Pn7hb1tt + QbPb0EOt4m0z7CTU0k16yypmP3R4+w1kni4KJqLww66tos1GauMtfKXDjSRtIA4l0dgGtR7aNBE82 + 5oCmrX0w1hEVLkCDzjYBdjCP+M+lqDTzPMXMmRxTdBNuLHBZlpOWNy0Z9M6LYoS/BzLzjrLuvQRUM + CPkrR9J2QPuQLpebQsKnFgBKtttcwe5GLzdoong9cLVOUHGiL0QatEc7GvsgZ8u+x6SXhDJDlap3K + 1nFd52NWhIDDBjsrF3gQ==; +Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) + by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) + id 1h61bH-0004MJ-ST; Mon, 18 Mar 2019 23:23:23 +0000 +Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]) + by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) + id 1h61bB-0004Lt-LJ + for linux-arm-kernel@lists.infradead.org; Mon, 18 Mar 2019 23:23:22 +0000 +Received: by mail-wm1-x344.google.com with SMTP id a188so14550973wmf.3 + for <linux-arm-kernel@lists.infradead.org>; + Mon, 18 Mar 2019 16:23:17 -0700 (PDT) +DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; + h=from:to:cc:subject:date:message-id:mime-version + :content-transfer-encoding; + bh=NgkgycOAutPIwHnXZGiuxniA3uvcp0YWgMh4155m5jM=; + b=sIxPnczXC6LZ8Nuatp9CwqTh+kMPdq1DeydDq03Y7JOGGZITyag0jU8RKTzXWtvN+i + 4zZtdAf16PV7AOfxiu2uJFQuRevS39dpUjowVJQgPb1LjOY03uzzoBzk57HQ/9Il5Qt3 + uZxXo6sRxXgssI+EvcggoPUatVMFQy6zLwo8DVs3mNCbtFiJ4/W1bE+2vYjVIetbN9PY + w2++/X0FUZocY0xc+46hZJnFnrIYd7a5K0Sc8Z31sAbC+54SWRlFpJrJJo4Yv2GFK+gb + fsnQWE8L9xUox0ndssND/fuUAOeZgaReMQonwSxvdhNPxUXxnwKCGNEY3GnUXX+83K2a + AVkA== +X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; + d=1e100.net; s=20161025; + h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version + :content-transfer-encoding; + bh=NgkgycOAutPIwHnXZGiuxniA3uvcp0YWgMh4155m5jM=; + b=FO8o351SBCPiidIgPz1Ovubpo6/n9gLt21bJFitAyCvYruNIFu+YPUTfbnqkjzS6ZB + XeH8IUFoiILRU5zOAtsyqEvvm2mNEjSZlMefWXMmMaLftSU/Fp3PI9JuSs13e7+fY4d2 + pN2iK6nvFPlMl5CDfHOxNx5gxMPEzGL8XlOaZBTVUssKP5kL5UeqC+7BJwZl/Z5EuXhw + jnSzSn1L+MOzedaX4SPZC3S/lNVXAH6QBW6r06z3n4aH20JfMS7lsmbUi0LR1vJIHhOe + p1rV0RV5Sv1pBvckRhfIIv76KVLBP6FQY4Q8rutmFYo7gVoIbnkNMnT2sqU5rP89t2IG + Ez5g== +X-Gm-Message-State: APjAAAVTaayWQNyKAXTz8OnNFFycoVzi7ddiZfAbCYHQzcjBMFlQHpPK + T7qwajPBVoorwvW5+VwD1vE= +X-Google-Smtp-Source: + APXvYqyklaLHE005LYV5tVa6uV4lfxi+pkvZ4R79N1xrAuzuYsDP3nz53oMQmiMTL+jTaq+hwlcC0Q== +X-Received: by 2002:a7b:ce92:: with SMTP id q18mr1064644wmj.80.1552951395286; + Mon, 18 Mar 2019 16:23:15 -0700 (PDT) +Received: from localhost (pD9E51D2D.dip0.t-ipconnect.de. [217.229.29.45]) + by smtp.gmail.com with ESMTPSA id e5sm16582805wrh.71.2019.03.18.16.23.14 + (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); + Mon, 18 Mar 2019 16:23:14 -0700 (PDT) +From: Thierry Reding <thierry.reding@gmail.com> +To: Thierry Reding <thierry.reding@gmail.com> +Subject: [PATCH] arm64: tegra: Add NVIDIA Jetson Nano Developer Kit support +Date: Tue, 19 Mar 2019 00:23:13 +0100 +Message-Id: <20190318232313.24270-1-thierry.reding@gmail.com> +X-Mailer: git-send-email 2.21.0 +MIME-Version: 1.0 +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20190318_162317_924900_0FAC7D5E +X-CRM114-Status: GOOD ( 15.39 ) +X-BeenThere: linux-arm-kernel@lists.infradead.org +X-Mailman-Version: 2.1.21 +Precedence: list +List-Id: <linux-arm-kernel.lists.infradead.org> +List-Unsubscribe: + <http://lists.infradead.org/mailman/options/linux-arm-kernel>, + <mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe> +List-Archive: <http://lists.infradead.org/pipermail/linux-arm-kernel/> +List-Post: <mailto:linux-arm-kernel@lists.infradead.org> +List-Help: <mailto:linux-arm-kernel-request@lists.infradead.org?subject=help> +List-Subscribe: + <http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>, + <mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe> +Cc: linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, + Jonathan Hunter <jonathanh@nvidia.com> +Content-Type: text/plain; charset="us-ascii" +Sender: "linux-arm-kernel" <linux-arm-kernel-bounces@lists.infradead.org> +Errors-To: + linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org +X-Virus-Scanned: ClamAV using ClamSMTP + +From: Thierry Reding <treding@nvidia.com> + +The Jetson Nano Developer Kit is a Tegra X1 based development board. It +is similar to Jetson TX1 but it is not pin compatible. It features 4 GB +of LPDDR4, an SPI NOR flash for early boot firmware and an SD card slot +used for storage. + +HDMI 2.0 or DP 1.2 are available for display, four USB ports (3 USB 2.0 +and 1 USB 3.0) can be used to attach a variety of peripherals and a PCI +Ethernet controller provides onboard network connectivity. + +A 40-pin header on the board can be used to extend the capabilities and +exposed interfaces of the Jetson Nano. + +Signed-off-by: Thierry Reding <treding@nvidia.com> +--- +This patch, along with some related patches can be found in the p3450 +branch in the following repository: + + https://github.com/thierryreding/linux + + arch/arm64/boot/dts/nvidia/Makefile | 1 + + .../boot/dts/nvidia/tegra210-p3450-0000.dts | 1911 +++++++++++++++++ + 2 files changed, 1912 insertions(+) + create mode 100644 arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts + +diff --git a/arch/arm64/boot/dts/nvidia/Makefile b/arch/arm64/boot/dts/nvidia/Makefile +index 6b8ab5568481..bcd018c3162b 100644 +--- a/arch/arm64/boot/dts/nvidia/Makefile ++++ b/arch/arm64/boot/dts/nvidia/Makefile +@@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra132-norrin.dtb + dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-0000.dtb + dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-2180.dtb + dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2571.dtb ++dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p3450-0000.dtb + dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-smaug.dtb + dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2894-0050-a08.dtb + dtb-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-p2771-0000.dtb +diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +new file mode 100644 +index 000000000000..b1d8a49ca8c4 +--- /dev/null ++++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +@@ -0,0 +1,1911 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/dts-v1/; ++ ++#include <dt-bindings/input/gpio-keys.h> ++#include <dt-bindings/input/linux-event-codes.h> ++#include <dt-bindings/mfd/max77620.h> ++ ++#include "tegra210.dtsi" ++ ++/ { ++ model = "NVIDIA Jetson Nano Developer Kit"; ++ compatible = "nvidia,p3450-0000", "nvidia,tegra210"; ++ ++ aliases { ++ ethernet = "/pcie@1003000/pci@2,0/ethernet@0,0"; ++ rtc0 = "/i2c@7000d000/pmic@3c"; ++ rtc1 = "/rtc@7000e000"; ++ serial0 = &uarta; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ memory { ++ device_type = "memory"; ++ reg = <0x0 0x80000000 0x1 0x0>; ++ }; ++ ++ pcie@1003000 { ++ status = "okay"; ++ ++ hvddio-pex-supply = <&vdd_1v8>; ++ dvddio-pex-supply = <&vdd_pex_1v05>; ++ vddio-pex-ctl-supply = <&vdd_1v8>; ++ ++ pci@1,0 { ++ phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>, ++ <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>, ++ <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>, ++ <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>; ++ phy-names = "pcie-0", "pcie-1", "pcie-2", "pcie-3"; ++ nvidia,num-lanes = <4>; ++ status = "okay"; ++ }; ++ ++ pci@2,0 { ++ phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; ++ phy-names = "pcie-0"; ++ status = "okay"; ++ ++ ethernet@0,0 { ++ reg = <0x000000 0 0 0 0>; ++ mac-address = [ 00 00 00 00 00 00 ]; ++ }; ++ }; ++ }; ++ ++ host1x@50000000 { ++ dpaux@54040000 { ++ status = "okay"; ++ }; ++ ++ sor@54580000 { ++ status = "okay"; ++ ++ avdd-io-supply = <&avdd_1v05>; ++ vdd-pll-supply = <&vdd_1v8>; ++ hdmi-supply = <&vdd_hdmi>; ++ ++ nvidia,ddc-i2c-bus = <&hdmi_ddc>; ++ nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1) ++ GPIO_ACTIVE_LOW>; ++ nvidia,xbar-cfg = <0 1 2 3 4>; ++ }; ++ }; ++ ++ gpu@57000000 { ++ vdd-supply = <&vdd_gpu>; ++ status = "okay"; ++ }; ++ ++ pinmux: pinmux@700008d4 { ++ pinctrl-names = "boot"; ++ pinctrl-0 = <&state_boot>; ++ ++ state_boot: pinmux { ++ pex_l0_rst_n_pa0 { ++ nvidia,pins = "pex_l0_rst_n_pa0"; ++ nvidia,function = "pe0"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ nvidia,io-hv = <TEGRA_PIN_DISABLE>; ++ }; ++ pex_l0_clkreq_n_pa1 { ++ nvidia,pins = "pex_l0_clkreq_n_pa1"; ++ nvidia,function = "pe0"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ nvidia,io-hv = <TEGRA_PIN_DISABLE>; ++ }; ++ pex_wake_n_pa2 { ++ nvidia,pins = "pex_wake_n_pa2"; ++ nvidia,function = "pe"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ nvidia,io-hv = <TEGRA_PIN_DISABLE>; ++ }; ++ pex_l1_rst_n_pa3 { ++ nvidia,pins = "pex_l1_rst_n_pa3"; ++ nvidia,function = "pe1"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ nvidia,io-hv = <TEGRA_PIN_DISABLE>; ++ }; ++ pex_l1_clkreq_n_pa4 { ++ nvidia,pins = "pex_l1_clkreq_n_pa4"; ++ nvidia,function = "pe1"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ nvidia,io-hv = <TEGRA_PIN_DISABLE>; ++ }; ++ sata_led_active_pa5 { ++ nvidia,pins = "sata_led_active_pa5"; ++ nvidia,pull = <TEGRA_PIN_PULL_UP>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ pa6 { ++ nvidia,pins = "pa6"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ dap1_fs_pb0 { ++ nvidia,pins = "dap1_fs_pb0"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ dap1_din_pb1 { ++ nvidia,pins = "dap1_din_pb1"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ dap1_dout_pb2 { ++ nvidia,pins = "dap1_dout_pb2"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ dap1_sclk_pb3 { ++ nvidia,pins = "dap1_sclk_pb3"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ spi2_mosi_pb4 { ++ nvidia,pins = "spi2_mosi_pb4"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ spi2_miso_pb5 { ++ nvidia,pins = "spi2_miso_pb5"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ spi2_sck_pb6 { ++ nvidia,pins = "spi2_sck_pb6"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ spi2_cs0_pb7 { ++ nvidia,pins = "spi2_cs0_pb7"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ spi1_mosi_pc0 { ++ nvidia,pins = "spi1_mosi_pc0"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ spi1_miso_pc1 { ++ nvidia,pins = "spi1_miso_pc1"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ spi1_sck_pc2 { ++ nvidia,pins = "spi1_sck_pc2"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ spi1_cs0_pc3 { ++ nvidia,pins = "spi1_cs0_pc3"; ++ nvidia,pull = <TEGRA_PIN_PULL_UP>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ spi1_cs1_pc4 { ++ nvidia,pins = "spi1_cs1_pc4"; ++ nvidia,pull = <TEGRA_PIN_PULL_UP>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ spi4_sck_pc5 { ++ nvidia,pins = "spi4_sck_pc5"; ++ nvidia,function = "rsvd1"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_ENABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ spi4_cs0_pc6 { ++ nvidia,pins = "spi4_cs0_pc6"; ++ nvidia,function = "rsvd1"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_ENABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ spi4_mosi_pc7 { ++ nvidia,pins = "spi4_mosi_pc7"; ++ nvidia,function = "rsvd1"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_ENABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ spi4_miso_pd0 { ++ nvidia,pins = "spi4_miso_pd0"; ++ nvidia,function = "rsvd1"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_ENABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ uart3_tx_pd1 { ++ nvidia,pins = "uart3_tx_pd1"; ++ nvidia,function = "uartc"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ uart3_rx_pd2 { ++ nvidia,pins = "uart3_rx_pd2"; ++ nvidia,function = "uartc"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ uart3_rts_pd3 { ++ nvidia,pins = "uart3_rts_pd3"; ++ nvidia,function = "uartc"; ++ nvidia,pull = <TEGRA_PIN_PULL_UP>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ uart3_cts_pd4 { ++ nvidia,pins = "uart3_cts_pd4"; ++ nvidia,function = "uartc"; ++ nvidia,pull = <TEGRA_PIN_PULL_UP>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ dmic1_clk_pe0 { ++ nvidia,pins = "dmic1_clk_pe0"; ++ nvidia,function = "i2s3"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ dmic1_dat_pe1 { ++ nvidia,pins = "dmic1_dat_pe1"; ++ nvidia,function = "i2s3"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ dmic2_clk_pe2 { ++ nvidia,pins = "dmic2_clk_pe2"; ++ nvidia,function = "i2s3"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ dmic2_dat_pe3 { ++ nvidia,pins = "dmic2_dat_pe3"; ++ nvidia,function = "i2s3"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ dmic3_clk_pe4 { ++ nvidia,pins = "dmic3_clk_pe4"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_ENABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ dmic3_dat_pe5 { ++ nvidia,pins = "dmic3_dat_pe5"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_ENABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ pe6 { ++ nvidia,pins = "pe6"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ pe7 { ++ nvidia,pins = "pe7"; ++ nvidia,function = "pwm3"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ gen3_i2c_scl_pf0 { ++ nvidia,pins = "gen3_i2c_scl_pf0"; ++ nvidia,function = "i2c3"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ nvidia,io-hv = <TEGRA_PIN_DISABLE>; ++ }; ++ gen3_i2c_sda_pf1 { ++ nvidia,pins = "gen3_i2c_sda_pf1"; ++ nvidia,function = "i2c3"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ nvidia,io-hv = <TEGRA_PIN_DISABLE>; ++ }; ++ uart2_tx_pg0 { ++ nvidia,pins = "uart2_tx_pg0"; ++ nvidia,function = "uartb"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ uart2_rx_pg1 { ++ nvidia,pins = "uart2_rx_pg1"; ++ nvidia,function = "uartb"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ uart2_rts_pg2 { ++ nvidia,pins = "uart2_rts_pg2"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ uart2_cts_pg3 { ++ nvidia,pins = "uart2_cts_pg3"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ wifi_en_ph0 { ++ nvidia,pins = "wifi_en_ph0"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ wifi_rst_ph1 { ++ nvidia,pins = "wifi_rst_ph1"; ++ nvidia,function = "rsvd0"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_ENABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ wifi_wake_ap_ph2 { ++ nvidia,pins = "wifi_wake_ap_ph2"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ ap_wake_bt_ph3 { ++ nvidia,pins = "ap_wake_bt_ph3"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ bt_rst_ph4 { ++ nvidia,pins = "bt_rst_ph4"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ bt_wake_ap_ph5 { ++ nvidia,pins = "bt_wake_ap_ph5"; ++ nvidia,pull = <TEGRA_PIN_PULL_UP>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ ph6 { ++ nvidia,pins = "ph6"; ++ nvidia,pull = <TEGRA_PIN_PULL_UP>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ ap_wake_nfc_ph7 { ++ nvidia,pins = "ap_wake_nfc_ph7"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ nfc_en_pi0 { ++ nvidia,pins = "nfc_en_pi0"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ nfc_int_pi1 { ++ nvidia,pins = "nfc_int_pi1"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ gps_en_pi2 { ++ nvidia,pins = "gps_en_pi2"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ gps_rst_pi3 { ++ nvidia,pins = "gps_rst_pi3"; ++ nvidia,function = "rsvd0"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_ENABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ uart4_tx_pi4 { ++ nvidia,pins = "uart4_tx_pi4"; ++ nvidia,function = "uartd"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ uart4_rx_pi5 { ++ nvidia,pins = "uart4_rx_pi5"; ++ nvidia,function = "uartd"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ uart4_rts_pi6 { ++ nvidia,pins = "uart4_rts_pi6"; ++ nvidia,function = "uartd"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ uart4_cts_pi7 { ++ nvidia,pins = "uart4_cts_pi7"; ++ nvidia,function = "uartd"; ++ nvidia,pull = <TEGRA_PIN_PULL_UP>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ gen1_i2c_sda_pj0 { ++ nvidia,pins = "gen1_i2c_sda_pj0"; ++ nvidia,function = "i2c1"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ nvidia,io-hv = <TEGRA_PIN_ENABLE>; ++ }; ++ gen1_i2c_scl_pj1 { ++ nvidia,pins = "gen1_i2c_scl_pj1"; ++ nvidia,function = "i2c1"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ nvidia,io-hv = <TEGRA_PIN_ENABLE>; ++ }; ++ gen2_i2c_scl_pj2 { ++ nvidia,pins = "gen2_i2c_scl_pj2"; ++ nvidia,function = "i2c2"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ nvidia,io-hv = <TEGRA_PIN_ENABLE>; ++ }; ++ gen2_i2c_sda_pj3 { ++ nvidia,pins = "gen2_i2c_sda_pj3"; ++ nvidia,function = "i2c2"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ nvidia,io-hv = <TEGRA_PIN_ENABLE>; ++ }; ++ dap4_fs_pj4 { ++ nvidia,pins = "dap4_fs_pj4"; ++ nvidia,function = "rsvd1"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_ENABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ dap4_din_pj5 { ++ nvidia,pins = "dap4_din_pj5"; ++ nvidia,function = "rsvd1"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_ENABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ dap4_dout_pj6 { ++ nvidia,pins = "dap4_dout_pj6"; ++ nvidia,function = "rsvd1"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_ENABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ dap4_sclk_pj7 { ++ nvidia,pins = "dap4_sclk_pj7"; ++ nvidia,function = "rsvd1"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_ENABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ pk0 { ++ nvidia,pins = "pk0"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_ENABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ pk1 { ++ nvidia,pins = "pk1"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_ENABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ pk2 { ++ nvidia,pins = "pk2"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_ENABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ pk3 { ++ nvidia,pins = "pk3"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_ENABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ pk4 { ++ nvidia,pins = "pk4"; ++ nvidia,function = "rsvd1"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_ENABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ pk5 { ++ nvidia,pins = "pk5"; ++ nvidia,function = "rsvd1"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_ENABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ pk6 { ++ nvidia,pins = "pk6"; ++ nvidia,function = "rsvd1"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_ENABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ pk7 { ++ nvidia,pins = "pk7"; ++ nvidia,function = "rsvd1"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_ENABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ pl0 { ++ nvidia,pins = "pl0"; ++ nvidia,function = "rsvd0"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_ENABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ pl1 { ++ nvidia,pins = "pl1"; ++ nvidia,function = "rsvd1"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_ENABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ sdmmc1_clk_pm0 { ++ nvidia,pins = "sdmmc1_clk_pm0"; ++ nvidia,function = "sdmmc1"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ sdmmc1_cmd_pm1 { ++ nvidia,pins = "sdmmc1_cmd_pm1"; ++ nvidia,function = "sdmmc1"; ++ nvidia,pull = <TEGRA_PIN_PULL_UP>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ sdmmc1_dat3_pm2 { ++ nvidia,pins = "sdmmc1_dat3_pm2"; ++ nvidia,function = "sdmmc1"; ++ nvidia,pull = <TEGRA_PIN_PULL_UP>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ sdmmc1_dat2_pm3 { ++ nvidia,pins = "sdmmc1_dat2_pm3"; ++ nvidia,function = "sdmmc1"; ++ nvidia,pull = <TEGRA_PIN_PULL_UP>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ sdmmc1_dat1_pm4 { ++ nvidia,pins = "sdmmc1_dat1_pm4"; ++ nvidia,function = "sdmmc1"; ++ nvidia,pull = <TEGRA_PIN_PULL_UP>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ sdmmc1_dat0_pm5 { ++ nvidia,pins = "sdmmc1_dat0_pm5"; ++ nvidia,function = "sdmmc1"; ++ nvidia,pull = <TEGRA_PIN_PULL_UP>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ sdmmc3_clk_pp0 { ++ nvidia,pins = "sdmmc3_clk_pp0"; ++ nvidia,function = "sdmmc3"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ sdmmc3_cmd_pp1 { ++ nvidia,pins = "sdmmc3_cmd_pp1"; ++ nvidia,function = "sdmmc3"; ++ nvidia,pull = <TEGRA_PIN_PULL_UP>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ sdmmc3_dat3_pp2 { ++ nvidia,pins = "sdmmc3_dat3_pp2"; ++ nvidia,function = "sdmmc3"; ++ nvidia,pull = <TEGRA_PIN_PULL_UP>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ sdmmc3_dat2_pp3 { ++ nvidia,pins = "sdmmc3_dat2_pp3"; ++ nvidia,function = "sdmmc3"; ++ nvidia,pull = <TEGRA_PIN_PULL_UP>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ sdmmc3_dat1_pp4 { ++ nvidia,pins = "sdmmc3_dat1_pp4"; ++ nvidia,function = "sdmmc3"; ++ nvidia,pull = <TEGRA_PIN_PULL_UP>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ sdmmc3_dat0_pp5 { ++ nvidia,pins = "sdmmc3_dat0_pp5"; ++ nvidia,function = "sdmmc3"; ++ nvidia,pull = <TEGRA_PIN_PULL_UP>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ cam1_mclk_ps0 { ++ nvidia,pins = "cam1_mclk_ps0"; ++ nvidia,function = "extperiph3"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ cam2_mclk_ps1 { ++ nvidia,pins = "cam2_mclk_ps1"; ++ nvidia,function = "extperiph3"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ cam_i2c_scl_ps2 { ++ nvidia,pins = "cam_i2c_scl_ps2"; ++ nvidia,function = "i2cvi"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ nvidia,io-hv = <TEGRA_PIN_ENABLE>; ++ }; ++ cam_i2c_sda_ps3 { ++ nvidia,pins = "cam_i2c_sda_ps3"; ++ nvidia,function = "i2cvi"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ nvidia,io-hv = <TEGRA_PIN_ENABLE>; ++ }; ++ cam_rst_ps4 { ++ nvidia,pins = "cam_rst_ps4"; ++ nvidia,function = "rsvd1"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_ENABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ cam_af_en_ps5 { ++ nvidia,pins = "cam_af_en_ps5"; ++ nvidia,pull = <TEGRA_PIN_PULL_UP>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ cam_flash_en_ps6 { ++ nvidia,pins = "cam_flash_en_ps6"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_ENABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ cam1_pwdn_ps7 { ++ nvidia,pins = "cam1_pwdn_ps7"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ cam2_pwdn_pt0 { ++ nvidia,pins = "cam2_pwdn_pt0"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ cam1_strobe_pt1 { ++ nvidia,pins = "cam1_strobe_pt1"; ++ nvidia,function = "rsvd1"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_ENABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ uart1_tx_pu0 { ++ nvidia,pins = "uart1_tx_pu0"; ++ nvidia,function = "uarta"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ uart1_rx_pu1 { ++ nvidia,pins = "uart1_rx_pu1"; ++ nvidia,function = "uarta"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ uart1_rts_pu2 { ++ nvidia,pins = "uart1_rts_pu2"; ++ nvidia,function = "uarta"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ uart1_cts_pu3 { ++ nvidia,pins = "uart1_cts_pu3"; ++ nvidia,function = "rsvd1"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_ENABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ lcd_bl_pwm_pv0 { ++ nvidia,pins = "lcd_bl_pwm_pv0"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ lcd_bl_en_pv1 { ++ nvidia,pins = "lcd_bl_en_pv1"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ lcd_rst_pv2 { ++ nvidia,pins = "lcd_rst_pv2"; ++ nvidia,function = "rsvd0"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_ENABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ lcd_gpio1_pv3 { ++ nvidia,pins = "lcd_gpio1_pv3"; ++ nvidia,function = "rsvd1"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_ENABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ lcd_gpio2_pv4 { ++ nvidia,pins = "lcd_gpio2_pv4"; ++ nvidia,function = "pwm1"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ ap_ready_pv5 { ++ nvidia,pins = "ap_ready_pv5"; ++ nvidia,function = "rsvd0"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_ENABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ touch_rst_pv6 { ++ nvidia,pins = "touch_rst_pv6"; ++ nvidia,function = "rsvd0"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_ENABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ touch_clk_pv7 { ++ nvidia,pins = "touch_clk_pv7"; ++ nvidia,function = "rsvd1"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_ENABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ modem_wake_ap_px0 { ++ nvidia,pins = "modem_wake_ap_px0"; ++ nvidia,function = "rsvd0"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_ENABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ touch_int_px1 { ++ nvidia,pins = "touch_int_px1"; ++ nvidia,function = "rsvd0"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_ENABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ motion_int_px2 { ++ nvidia,pins = "motion_int_px2"; ++ nvidia,function = "rsvd0"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_ENABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ als_prox_int_px3 { ++ nvidia,pins = "als_prox_int_px3"; ++ nvidia,pull = <TEGRA_PIN_PULL_UP>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ temp_alert_px4 { ++ nvidia,pins = "temp_alert_px4"; ++ nvidia,pull = <TEGRA_PIN_PULL_UP>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ button_power_on_px5 { ++ nvidia,pins = "button_power_on_px5"; ++ nvidia,pull = <TEGRA_PIN_PULL_UP>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ button_vol_up_px6 { ++ nvidia,pins = "button_vol_up_px6"; ++ nvidia,pull = <TEGRA_PIN_PULL_UP>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ button_vol_down_px7 { ++ nvidia,pins = "button_vol_down_px7"; ++ nvidia,function = "rsvd0"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_ENABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ button_slide_sw_py0 { ++ nvidia,pins = "button_slide_sw_py0"; ++ nvidia,function = "rsvd0"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_ENABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ button_home_py1 { ++ nvidia,pins = "button_home_py1"; ++ nvidia,pull = <TEGRA_PIN_PULL_UP>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ lcd_te_py2 { ++ nvidia,pins = "lcd_te_py2"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ pwr_i2c_scl_py3 { ++ nvidia,pins = "pwr_i2c_scl_py3"; ++ nvidia,function = "i2cpmu"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ nvidia,io-hv = <TEGRA_PIN_DISABLE>; ++ }; ++ pwr_i2c_sda_py4 { ++ nvidia,pins = "pwr_i2c_sda_py4"; ++ nvidia,function = "i2cpmu"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ nvidia,io-hv = <TEGRA_PIN_DISABLE>; ++ }; ++ clk_32k_out_py5 { ++ nvidia,pins = "clk_32k_out_py5"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_ENABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ pz0 { ++ nvidia,pins = "pz0"; ++ nvidia,pull = <TEGRA_PIN_PULL_UP>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ pz1 { ++ nvidia,pins = "pz1"; ++ nvidia,function = "sdmmc1"; ++ nvidia,pull = <TEGRA_PIN_PULL_UP>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ pz2 { ++ nvidia,pins = "pz2"; ++ nvidia,pull = <TEGRA_PIN_PULL_UP>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ pz3 { ++ nvidia,pins = "pz3"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ pz4 { ++ nvidia,pins = "pz4"; ++ nvidia,function = "rsvd1"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_ENABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ pz5 { ++ nvidia,pins = "pz5"; ++ nvidia,function = "soc"; ++ nvidia,pull = <TEGRA_PIN_PULL_UP>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ dap2_fs_paa0 { ++ nvidia,pins = "dap2_fs_paa0"; ++ nvidia,function = "i2s2"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ dap2_sclk_paa1 { ++ nvidia,pins = "dap2_sclk_paa1"; ++ nvidia,function = "i2s2"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ dap2_din_paa2 { ++ nvidia,pins = "dap2_din_paa2"; ++ nvidia,function = "i2s2"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ dap2_dout_paa3 { ++ nvidia,pins = "dap2_dout_paa3"; ++ nvidia,function = "i2s2"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ aud_mclk_pbb0 { ++ nvidia,pins = "aud_mclk_pbb0"; ++ nvidia,pull = <TEGRA_PIN_PULL_UP>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ dvfs_pwm_pbb1 { ++ nvidia,pins = "dvfs_pwm_pbb1"; ++ nvidia,function = "cldvfs"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_ENABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ dvfs_clk_pbb2 { ++ nvidia,pins = "dvfs_clk_pbb2"; ++ nvidia,function = "rsvd0"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_ENABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ gpio_x1_aud_pbb3 { ++ nvidia,pins = "gpio_x1_aud_pbb3"; ++ nvidia,function = "rsvd0"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_ENABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ gpio_x3_aud_pbb4 { ++ nvidia,pins = "gpio_x3_aud_pbb4"; ++ nvidia,function = "rsvd0"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_ENABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ hdmi_cec_pcc0 { ++ nvidia,pins = "hdmi_cec_pcc0"; ++ nvidia,function = "cec"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ nvidia,io-hv = <TEGRA_PIN_ENABLE>; ++ }; ++ hdmi_int_dp_hpd_pcc1 { ++ nvidia,pins = "hdmi_int_dp_hpd_pcc1"; ++ nvidia,function = "dp"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ nvidia,io-hv = <TEGRA_PIN_DISABLE>; ++ }; ++ spdif_out_pcc2 { ++ nvidia,pins = "spdif_out_pcc2"; ++ nvidia,function = "rsvd1"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_ENABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ spdif_in_pcc3 { ++ nvidia,pins = "spdif_in_pcc3"; ++ nvidia,function = "rsvd1"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_ENABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ usb_vbus_en0_pcc4 { ++ nvidia,pins = "usb_vbus_en0_pcc4"; ++ nvidia,pull = <TEGRA_PIN_PULL_UP>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ nvidia,io-hv = <TEGRA_PIN_DISABLE>; ++ }; ++ usb_vbus_en1_pcc5 { ++ nvidia,pins = "usb_vbus_en1_pcc5"; ++ nvidia,function = "rsvd1"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_ENABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ nvidia,io-hv = <TEGRA_PIN_DISABLE>; ++ }; ++ dp_hpd0_pcc6 { ++ nvidia,pins = "dp_hpd0_pcc6"; ++ nvidia,function = "dp"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ pcc7 { ++ nvidia,pins = "pcc7"; ++ nvidia,function = "rsvd0"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_ENABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ nvidia,io-hv = <TEGRA_PIN_DISABLE>; ++ }; ++ spi2_cs1_pdd0 { ++ nvidia,pins = "spi2_cs1_pdd0"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ qspi_sck_pee0 { ++ nvidia,pins = "qspi_sck_pee0"; ++ nvidia,function = "qspi"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ qspi_cs_n_pee1 { ++ nvidia,pins = "qspi_cs_n_pee1"; ++ nvidia,function = "qspi"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ qspi_io0_pee2 { ++ nvidia,pins = "qspi_io0_pee2"; ++ nvidia,function = "qspi"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ qspi_io1_pee3 { ++ nvidia,pins = "qspi_io1_pee3"; ++ nvidia,function = "qspi"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ qspi_io2_pee4 { ++ nvidia,pins = "qspi_io2_pee4"; ++ nvidia,function = "rsvd1"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_ENABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ qspi_io3_pee5 { ++ nvidia,pins = "qspi_io3_pee5"; ++ nvidia,function = "rsvd1"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_ENABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ core_pwr_req { ++ nvidia,pins = "core_pwr_req"; ++ nvidia,function = "core"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ cpu_pwr_req { ++ nvidia,pins = "cpu_pwr_req"; ++ nvidia,function = "rsvd1"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_ENABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ pwr_int_n { ++ nvidia,pins = "pwr_int_n"; ++ nvidia,function = "pmi"; ++ nvidia,pull = <TEGRA_PIN_PULL_UP>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ clk_32k_in { ++ nvidia,pins = "clk_32k_in"; ++ nvidia,function = "clk"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_ENABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ jtag_rtck { ++ nvidia,pins = "jtag_rtck"; ++ nvidia,function = "jtag"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ clk_req { ++ nvidia,pins = "clk_req"; ++ nvidia,function = "rsvd1"; ++ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; ++ nvidia,tristate = <TEGRA_PIN_ENABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ shutdown { ++ nvidia,pins = "shutdown"; ++ nvidia,function = "shutdown"; ++ nvidia,pull = <TEGRA_PIN_PULL_NONE>; ++ nvidia,tristate = <TEGRA_PIN_DISABLE>; ++ nvidia,enable-input = <TEGRA_PIN_DISABLE>; ++ nvidia,open-drain = <TEGRA_PIN_DISABLE>; ++ }; ++ }; ++ }; ++ ++ /* debug port */ ++ serial@70006000 { ++ status = "okay"; ++ }; ++ ++ hdmi_ddc: i2c@7000c700 { ++ status = "okay"; ++ clock-frequency = <100000>; ++ }; ++ ++ i2c@7000d000 { ++ status = "okay"; ++ clock-frequency = <400000>; ++ ++ pmic: pmic@3c { ++ compatible = "maxim,max77620"; ++ reg = <0x3c>; ++ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; ++ ++ #interrupt-cells = <2>; ++ interrupt-controller; ++ ++ #gpio-cells = <2>; ++ gpio-controller; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&max77620_default>; ++ ++ max77620_default: pinmux { ++ gpio0 { ++ pins = "gpio0"; ++ function = "gpio"; ++ }; ++ ++ gpio1 { ++ pins = "gpio1"; ++ function = "fps-out"; ++ drive-push-pull = <1>; ++ maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; ++ maxim,active-fps-power-up-slot = <0>; ++ maxim,active-fps-power-down-slot = <7>; ++ }; ++ ++ gpio2 { ++ pins = "gpio2"; ++ function = "fps-out"; ++ drive-open-drain = <1>; ++ maxim,active-fps-source = <MAX77620_FPS_SRC_0>; ++ maxim,active-fps-power-up-slot = <0>; ++ maxim,active-fps-power-down-slot = <7>; ++ }; ++ ++ gpio3 { ++ pins = "gpio3"; ++ function = "fps-out"; ++ drive-open-drain = <1>; ++ maxim,active-fps-source = <MAX77620_FPS_SRC_0>; ++ maxim,active-fps-power-up-slot = <4>; ++ maxim,active-fps-power-down-slot = <3>; ++ }; ++ ++ gpio4 { ++ pins = "gpio4"; ++ function = "32k-out1"; ++ }; ++ ++ gpio5_6_7 { ++ pins = "gpio5", "gpio6", "gpio7"; ++ function = "gpio"; ++ drive-push-pull = <1>; ++ }; ++ }; ++ ++ fps { ++ fps0 { ++ maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; ++ maxim,suspend-fps-time-period-us = <5120>; ++ }; ++ ++ fps1 { ++ maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; ++ maxim,suspend-fps-time-period-us = <5120>; ++ }; ++ ++ fps2 { ++ maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; ++ }; ++ }; ++ ++ regulators { ++ in-ldo0-1-supply = <&vdd_pre>; ++ in-ldo2-supply = <&vdd_3v3_sys>; ++ in-ldo3-5-supply = <&vdd_1v8>; ++ in-ldo4-6-supply = <&vdd_5v0_sys>; ++ in-ldo7-8-supply = <&vdd_pre>; ++ in-sd0-supply = <&vdd_5v0_sys>; ++ in-sd1-supply = <&vdd_5v0_sys>; ++ in-sd2-supply = <&vdd_5v0_sys>; ++ in-sd3-supply = <&vdd_5v0_sys>; ++ ++ vdd_soc: sd0 { ++ regulator-name = "VDD_SOC"; ++ regulator-min-microvolt = <1000000>; ++ regulator-max-microvolt = <1170000>; ++ regulator-enable-ramp-delay = <146>; ++ regulator-disable-ramp-delay = <4080>; ++ regulator-ramp-delay = <27500>; ++ regulator-ramp-delay-scale = <300>; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ maxim,active-fps-source = <MAX77620_FPS_SRC_1>; ++ maxim,active-fps-power-up-slot = <1>; ++ maxim,active-fps-power-down-slot = <6>; ++ }; ++ ++ vdd_ddr: sd1 { ++ regulator-name = "VDD_DDR_1V1_PMIC"; ++ regulator-min-microvolt = <1150000>; ++ regulator-max-microvolt = <1150000>; ++ regulator-enable-ramp-delay = <176>; ++ regulator-disable-ramp-delay = <145800>; ++ regulator-ramp-delay = <27500>; ++ regulator-ramp-delay-scale = <300>; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ maxim,active-fps-source = <MAX77620_FPS_SRC_0>; ++ maxim,active-fps-power-up-slot = <5>; ++ maxim,active-fps-power-down-slot = <2>; ++ }; ++ ++ vdd_pre: sd2 { ++ regulator-name = "VDD_PRE_REG_1V35"; ++ regulator-min-microvolt = <1350000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-enable-ramp-delay = <176>; ++ regulator-disable-ramp-delay = <32000>; ++ regulator-ramp-delay = <27500>; ++ regulator-ramp-delay-scale = <350>; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ maxim,active-fps-source = <MAX77620_FPS_SRC_1>; ++ maxim,active-fps-power-up-slot = <2>; ++ maxim,active-fps-power-down-slot = <5>; ++ }; ++ ++ vdd_1v8: sd3 { ++ regulator-name = "VDD_1V8"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-enable-ramp-delay = <242>; ++ regulator-disable-ramp-delay = <118000>; ++ regulator-ramp-delay = <27500>; ++ regulator-ramp-delay-scale = <360>; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ maxim,active-fps-source = <MAX77620_FPS_SRC_0>; ++ maxim,active-fps-power-up-slot = <3>; ++ maxim,active-fps-power-down-slot = <4>; ++ }; ++ ++ vdd_sys_1v2: ldo0 { ++ regulator-name = "AVDD_SYS_1V2"; ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-enable-ramp-delay = <26>; ++ regulator-disable-ramp-delay = <626>; ++ regulator-ramp-delay = <100000>; ++ regulator-ramp-delay-scale = <200>; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; ++ maxim,active-fps-power-up-slot = <0>; ++ maxim,active-fps-power-down-slot = <7>; ++ }; ++ ++ vdd_pex_1v05: ldo1 { ++ regulator-name = "VDD_PEX_1V05"; ++ regulator-min-microvolt = <1050000>; ++ regulator-max-microvolt = <1050000>; ++ regulator-enable-ramp-delay = <22>; ++ regulator-disable-ramp-delay = <650>; ++ regulator-ramp-delay = <100000>; ++ regulator-ramp-delay-scale = <200>; ++ ++ maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; ++ maxim,active-fps-power-up-slot = <0>; ++ maxim,active-fps-power-down-slot = <7>; ++ }; ++ ++ vddio_sdmmc: ldo2 { ++ regulator-name = "VDDIO_SDMMC"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-enable-ramp-delay = <62>; ++ regulator-disable-ramp-delay = <650>; ++ regulator-ramp-delay = <100000>; ++ regulator-ramp-delay-scale = <200>; ++ ++ maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; ++ maxim,active-fps-power-up-slot = <0>; ++ maxim,active-fps-power-down-slot = <7>; ++ }; ++ ++ ldo3 { ++ status = "disabled"; ++ }; ++ ++ vdd_rtc: ldo4 { ++ regulator-name = "VDD_RTC"; ++ regulator-min-microvolt = <850000>; ++ regulator-max-microvolt = <1100000>; ++ regulator-enable-ramp-delay = <22>; ++ regulator-disable-ramp-delay = <610>; ++ regulator-ramp-delay = <100000>; ++ regulator-ramp-delay-scale = <200>; ++ regulator-disable-active-discharge; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ maxim,active-fps-source = <MAX77620_FPS_SRC_0>; ++ maxim,active-fps-power-up-slot = <1>; ++ maxim,active-fps-power-down-slot = <6>; ++ }; ++ ++ ldo5 { ++ status = "disabled"; ++ }; ++ ++ ldo6 { ++ status = "disabled"; ++ }; ++ ++ avdd_1v05_pll: ldo7 { ++ regulator-name = "AVDD_1V05_PLL"; ++ regulator-min-microvolt = <1050000>; ++ regulator-max-microvolt = <1050000>; ++ regulator-enable-ramp-delay = <24>; ++ regulator-disable-ramp-delay = <2768>; ++ regulator-ramp-delay = <100000>; ++ regulator-ramp-delay-scale = <200>; ++ ++ maxim,active-fps-source = <MAX77620_FPS_SRC_1>; ++ maxim,active-fps-power-up-slot = <3>; ++ maxim,active-fps-power-down-slot = <4>; ++ }; ++ ++ avdd_1v05: ldo8 { ++ regulator-name = "AVDD_SATA_HDMI_DP_1V05"; ++ regulator-min-microvolt = <1050000>; ++ regulator-max-microvolt = <1050000>; ++ regulator-enable-ramp-delay = <22>; ++ regulator-disable-ramp-delay = <1160>; ++ regulator-ramp-delay = <100000>; ++ regulator-ramp-delay-scale = <200>; ++ ++ maxim,active-fps-source = <MAX77620_FPS_SRC_1>; ++ maxim,active-fps-power-up-slot = <6>; ++ maxim,active-fps-power-down-slot = <1>; ++ }; ++ }; ++ }; ++ }; ++ ++ pmc@7000e400 { ++ nvidia,invert-interrupt; ++ }; ++ ++ hda@70030000 { ++ status = "okay"; ++ }; ++ ++ usb@70090000 { ++ phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, ++ <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, ++ <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, ++ <&{/padctl@7009f000/pads/pcie/lanes/pcie-6}>; ++ phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0"; ++ ++ avdd-usb-supply = <&vdd_3v3_sys>; ++ dvddio-pex-supply = <&vdd_pex_1v05>; ++ hvddio-pex-supply = <&vdd_1v8>; ++ ++ status = "okay"; ++ }; ++ ++ padctl@7009f000 { ++ status = "okay"; ++ ++ avdd-pll-utmip-supply = <&vdd_1v8>; ++ avdd-pll-uerefe-supply = <&vdd_pex_1v05>; ++ dvdd-pex-pll-supply = <&vdd_pex_1v05>; ++ hvdd-pex-pll-e-supply = <&vdd_1v8>; ++ ++ pads { ++ usb2 { ++ status = "okay"; ++ ++ lanes { ++ usb2-0 { ++ nvidia,function = "xusb"; ++ status = "okay"; ++ }; ++ ++ usb2-1 { ++ nvidia,function = "xusb"; ++ status = "okay"; ++ }; ++ ++ usb2-2 { ++ nvidia,function = "xusb"; ++ status = "okay"; ++ }; ++ }; ++ }; ++ ++ pcie { ++ status = "okay"; ++ ++ lanes { ++ pcie-0 { ++ nvidia,function = "pcie-x1"; ++ status = "okay"; ++ }; ++ ++ pcie-1 { ++ nvidia,function = "pcie-x4"; ++ status = "okay"; ++ }; ++ ++ pcie-2 { ++ nvidia,function = "pcie-x4"; ++ status = "okay"; ++ }; ++ ++ pcie-3 { ++ nvidia,function = "pcie-x4"; ++ status = "okay"; ++ }; ++ ++ pcie-4 { ++ nvidia,function = "pcie-x4"; ++ status = "okay"; ++ }; ++ ++ pcie-5 { ++ nvidia,function = "usb3-ss"; ++ status = "okay"; ++ }; ++ ++ pcie-6 { ++ nvidia,function = "usb3-ss"; ++ status = "okay"; ++ }; ++ }; ++ }; ++ }; ++ ++ ports { ++ usb2-0 { ++ status = "okay"; ++ mode = "otg"; ++ }; ++ ++ usb2-1 { ++ status = "okay"; ++ mode = "host"; ++ }; ++ ++ usb2-2 { ++ status = "okay"; ++ mode = "host"; ++ }; ++ ++ usb3-0 { ++ status = "okay"; ++ nvidia,usb2-companion = <1>; ++ vbus-supply = <&vdd_hub_3v3>; ++ }; ++ }; ++ }; ++ ++ sdhci@700b0000 { ++ status = "okay"; ++ bus-width = <4>; ++ ++ cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; ++ ++ vqmmc-supply = <&vddio_sdmmc>; ++ vmmc-supply = <&vdd_3v3_sd>; ++ }; ++ ++ clocks { ++ compatible = "simple-bus"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ clk32k_in: clock@0 { ++ compatible = "fixed-clock"; ++ reg = <0>; ++ #clock-cells = <0>; ++ clock-frequency = <32768>; ++ }; ++ }; ++ ++ cpus { ++ cpu@0 { ++ enable-method = "psci"; ++ }; ++ ++ cpu@1 { ++ enable-method = "psci"; ++ }; ++ ++ cpu@2 { ++ enable-method = "psci"; ++ }; ++ ++ cpu@3 { ++ enable-method = "psci"; ++ }; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ ++ power { ++ label = "Power"; ++ gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW>; ++ linux,input-type = <EV_KEY>; ++ linux,code = <KEY_POWER>; ++ debounce-interval = <30>; ++ wakeup-event-action = <EV_ACT_ASSERTED>; ++ wakeup-source; ++ }; ++ ++ force-recovery { ++ label = "Force Recovery"; ++ gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>; ++ linux,input-type = <EV_KEY>; ++ linux,code = <BTN_1>; ++ debounce-interval = <30>; ++ }; ++ }; ++ ++ psci { ++ compatible = "arm,psci-1.0"; ++ method = "smc"; ++ }; ++ ++ regulators { ++ compatible = "simple-bus"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ vdd_5v0_sys: regulator@0 { ++ compatible = "regulator-fixed"; ++ reg = <0>; ++ ++ regulator-name = "VDD_5V0_SYS"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ vdd_3v3_sys: regulator@1 { ++ compatible = "regulator-fixed"; ++ reg = <1>; ++ regulator-name = "VDD_3V3_SYS"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-enable-ramp-delay = <240>; ++ regulator-disable-ramp-delay = <11340>; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ gpio = <&pmic 3 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ ++ vin-supply = <&vdd_5v0_sys>; ++ }; ++ ++ vdd_3v3_sd: regulator@2 { ++ compatible = "regulator-fixed"; ++ reg = <2>; ++ ++ regulator-name = "VDD_3V3_SD"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ gpio = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ ++ vin-supply = <&vdd_3v3_sys>; ++ }; ++ ++ vdd_hdmi: regulator@3 { ++ compatible = "regulator-fixed"; ++ reg = <3>; ++ ++ regulator-name = "VDD_HDMI_5V0"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ ++ vin-supply = <&vdd_5v0_sys>; ++ }; ++ ++ vdd_hub_3v3: regulator@4 { ++ compatible = "regulator-fixed"; ++ reg = <4>; ++ ++ regulator-name = "VDD_HUB_3V3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ gpio = <&gpio TEGRA_GPIO(A, 6) GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ ++ vin-supply = <&vdd_5v0_sys>; ++ }; ++ ++ vdd_cpu: regulator@5 { ++ compatible = "regulator-fixed"; ++ reg = <5>; ++ ++ regulator-name = "VDD_CPU"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ gpio = <&pmic 5 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ ++ vin-supply = <&vdd_5v0_sys>; ++ }; ++ ++ vdd_gpu: regulator@6 { ++ compatible = "regulator-fixed"; ++ reg = <6>; ++ ++ regulator-name = "VDD_GPU"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-enable-ramp-delay = <250>; ++ ++ gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ ++ vin-supply = <&vdd_5v0_sys>; ++ }; ++ }; ++}; diff --git a/arm64-tegra-jetson-tx1-fixes.patch b/arm64-tegra-jetson-tx1-fixes.patch new file mode 100644 index 000000000..4ac5ea22a --- /dev/null +++ b/arm64-tegra-jetson-tx1-fixes.patch @@ -0,0 +1,68 @@ +From 005e0b987019fff6013dff99f44d9f6ce68f08ad Mon Sep 17 00:00:00 2001 +From: Peter Robinson <pbrobinson@gmail.com> +Date: Sat, 23 Mar 2019 17:42:18 +0000 +Subject: [PATCH 1/3] arm64: tegra210: Jetson TX1: disable WP to make SD card + work + +There's some issue with Write Protect detection on the Jetson TX1 +so just apply a quirk to disable the check for the time being. + +Signed-off-by: Peter Robinson <pbrobinson@gmail.com> +--- + arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi +index a96e6ee70c21..072788646cbf 100644 +--- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi ++++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi +@@ -1456,6 +1456,7 @@ + sdhci@700b0000 { + status = "okay"; + bus-width = <4>; ++ disable-wp; + + cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; + +-- +2.20.1 + +From aea4a7a551fd7342299d34f04a8b75f58644ac07 Mon Sep 17 00:00:00 2001 +From: Peter Robinson <pbrobinson@gmail.com> +Date: Sat, 23 Mar 2019 17:45:10 +0000 +Subject: [PATCH 2/3] arm64: tegra210: Jetson TX1: disable display panel and + associated backlight + +The Jetson TX1 dev kit doesn't ship with a screen by default and if +it's not there it appears to crash on boot so disable them both by +default until we work out the problem. + +Signed-off-by: Peter Robinson <pbrobinson@gmail.com> +--- + arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts +index 37e3c46e753f..a16f24f1d5ff 100644 +--- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts ++++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts +@@ -36,7 +36,7 @@ + + host1x@50000000 { + dsi@54300000 { +- status = "okay"; ++ status = "disabled"; + + avdd-dsi-csi-supply = <&vdd_dsi_csi>; + +@@ -54,6 +54,8 @@ + + i2c@7000c400 { + backlight: backlight@2c { ++ status = "disabled"; ++ + compatible = "ti,lp8557"; + reg = <0x2c>; + +-- +2.20.1 diff --git a/configs/fedora/generic/CONFIG_CHARLCD_BL_FLASH b/configs/fedora/generic/CONFIG_CHARLCD_BL_FLASH new file mode 100644 index 000000000..e94ac2650 --- /dev/null +++ b/configs/fedora/generic/CONFIG_CHARLCD_BL_FLASH @@ -0,0 +1 @@ +CONFIG_CHARLCD_BL_FLASH=y diff --git a/configs/fedora/generic/CONFIG_CHARLCD_BL_OFF b/configs/fedora/generic/CONFIG_CHARLCD_BL_OFF new file mode 100644 index 000000000..5f11fc1e0 --- /dev/null +++ b/configs/fedora/generic/CONFIG_CHARLCD_BL_OFF @@ -0,0 +1 @@ +# CONFIG_CHARLCD_BL_OFF is not set diff --git a/configs/fedora/generic/CONFIG_CHARLCD_BL_ON b/configs/fedora/generic/CONFIG_CHARLCD_BL_ON new file mode 100644 index 000000000..56c1e7cda --- /dev/null +++ b/configs/fedora/generic/CONFIG_CHARLCD_BL_ON @@ -0,0 +1 @@ +# CONFIG_CHARLCD_BL_ON is not set diff --git a/configs/fedora/generic/CONFIG_PANEL_CHANGE_MESSAGE b/configs/fedora/generic/CONFIG_PANEL_CHANGE_MESSAGE new file mode 100644 index 000000000..fb2a2555e --- /dev/null +++ b/configs/fedora/generic/CONFIG_PANEL_CHANGE_MESSAGE @@ -0,0 +1 @@ +# CONFIG_PANEL_CHANGE_MESSAGE is not set diff --git a/configs/fedora/generic/CONFIG_PARPORT_PANEL b/configs/fedora/generic/CONFIG_PARPORT_PANEL new file mode 100644 index 000000000..6e173ccd0 --- /dev/null +++ b/configs/fedora/generic/CONFIG_PARPORT_PANEL @@ -0,0 +1 @@ +# CONFIG_PARPORT_PANEL is not set diff --git a/kernel-aarch64-debug.config b/kernel-aarch64-debug.config index c9ff6cf6f..b4b4a4e74 100644 --- a/kernel-aarch64-debug.config +++ b/kernel-aarch64-debug.config @@ -880,6 +880,9 @@ CONFIG_CHARGER_QCOM_SMBB=m # CONFIG_CHARGER_RT9455 is not set # CONFIG_CHARGER_SBS is not set CONFIG_CHARGER_SMB347=m +CONFIG_CHARLCD_BL_FLASH=y +# CONFIG_CHARLCD_BL_OFF is not set +# CONFIG_CHARLCD_BL_ON is not set # CONFIG_CHASH_SELFTEST is not set # CONFIG_CHASH_STATS is not set CONFIG_CHECKPOINT_RESTORE=y @@ -4176,6 +4179,7 @@ CONFIG_PACKET=y # CONFIG_PAGE_EXTENSION is not set # CONFIG_PAGE_OWNER is not set # CONFIG_PAGE_POISONING is not set +# CONFIG_PANEL_CHANGE_MESSAGE is not set # CONFIG_PANEL is not set # CONFIG_PANIC_ON_OOPS is not set CONFIG_PANIC_TIMEOUT=0 @@ -4185,6 +4189,7 @@ CONFIG_PARAVIRT=y # CONFIG_PARIDE is not set CONFIG_PARMAN=m # CONFIG_PARPORT is not set +# CONFIG_PARPORT_PANEL is not set # CONFIG_PARPORT_PC is not set CONFIG_PARTITION_ADVANCED=y CONFIG_PATA_ACPI=m diff --git a/kernel-aarch64.config b/kernel-aarch64.config index bc29b8354..3e9ddf442 100644 --- a/kernel-aarch64.config +++ b/kernel-aarch64.config @@ -880,6 +880,9 @@ CONFIG_CHARGER_QCOM_SMBB=m # CONFIG_CHARGER_RT9455 is not set # CONFIG_CHARGER_SBS is not set CONFIG_CHARGER_SMB347=m +CONFIG_CHARLCD_BL_FLASH=y +# CONFIG_CHARLCD_BL_OFF is not set +# CONFIG_CHARLCD_BL_ON is not set # CONFIG_CHASH_SELFTEST is not set # CONFIG_CHASH_STATS is not set CONFIG_CHECKPOINT_RESTORE=y @@ -4156,6 +4159,7 @@ CONFIG_PACKET=y # CONFIG_PAGE_EXTENSION is not set # CONFIG_PAGE_OWNER is not set # CONFIG_PAGE_POISONING is not set +# CONFIG_PANEL_CHANGE_MESSAGE is not set # CONFIG_PANEL is not set # CONFIG_PANIC_ON_OOPS is not set CONFIG_PANIC_TIMEOUT=0 @@ -4165,6 +4169,7 @@ CONFIG_PARAVIRT=y # CONFIG_PARIDE is not set CONFIG_PARMAN=m # CONFIG_PARPORT is not set +# CONFIG_PARPORT_PANEL is not set # CONFIG_PARPORT_PC is not set CONFIG_PARTITION_ADVANCED=y CONFIG_PATA_ACPI=m diff --git a/kernel-armv7hl-debug.config b/kernel-armv7hl-debug.config index 74680b57e..a14f81189 100644 --- a/kernel-armv7hl-debug.config +++ b/kernel-armv7hl-debug.config @@ -894,6 +894,9 @@ CONFIG_CHARGER_SMB347=m CONFIG_CHARGER_TPS65090=m CONFIG_CHARGER_TPS65217=m CONFIG_CHARGER_TWL4030=m +CONFIG_CHARLCD_BL_FLASH=y +# CONFIG_CHARLCD_BL_OFF is not set +# CONFIG_CHARLCD_BL_ON is not set # CONFIG_CHASH_SELFTEST is not set # CONFIG_CHASH_STATS is not set CONFIG_CHECKPOINT_RESTORE=y @@ -4333,6 +4336,7 @@ CONFIG_PACKET=y # CONFIG_PAGE_OWNER is not set # CONFIG_PAGE_POISONING is not set CONFIG_PALMAS_GPADC=m +# CONFIG_PANEL_CHANGE_MESSAGE is not set # CONFIG_PANEL is not set # CONFIG_PANIC_ON_OOPS is not set CONFIG_PANIC_TIMEOUT=0 @@ -4342,6 +4346,7 @@ CONFIG_PARAVIRT=y # CONFIG_PARIDE is not set CONFIG_PARMAN=m # CONFIG_PARPORT is not set +# CONFIG_PARPORT_PANEL is not set # CONFIG_PARPORT_PC is not set CONFIG_PARTITION_ADVANCED=y # CONFIG_PATA_ALI is not set diff --git a/kernel-armv7hl-lpae-debug.config b/kernel-armv7hl-lpae-debug.config index c9cd68dd9..492622199 100644 --- a/kernel-armv7hl-lpae-debug.config +++ b/kernel-armv7hl-lpae-debug.config @@ -865,6 +865,9 @@ CONFIG_CHARGER_MAX8997=m # CONFIG_CHARGER_SBS is not set CONFIG_CHARGER_SMB347=m CONFIG_CHARGER_TPS65090=m +CONFIG_CHARLCD_BL_FLASH=y +# CONFIG_CHARLCD_BL_OFF is not set +# CONFIG_CHARLCD_BL_ON is not set # CONFIG_CHASH_SELFTEST is not set # CONFIG_CHASH_STATS is not set CONFIG_CHECKPOINT_RESTORE=y @@ -4145,6 +4148,7 @@ CONFIG_PACKET=y # CONFIG_PAGE_EXTENSION is not set # CONFIG_PAGE_OWNER is not set # CONFIG_PAGE_POISONING is not set +# CONFIG_PANEL_CHANGE_MESSAGE is not set # CONFIG_PANEL is not set # CONFIG_PANIC_ON_OOPS is not set CONFIG_PANIC_TIMEOUT=0 @@ -4154,6 +4158,7 @@ CONFIG_PARAVIRT=y # CONFIG_PARIDE is not set CONFIG_PARMAN=m # CONFIG_PARPORT is not set +# CONFIG_PARPORT_PANEL is not set # CONFIG_PARPORT_PC is not set CONFIG_PARTITION_ADVANCED=y # CONFIG_PATA_ALI is not set diff --git a/kernel-armv7hl-lpae.config b/kernel-armv7hl-lpae.config index ac46efb01..df7505392 100644 --- a/kernel-armv7hl-lpae.config +++ b/kernel-armv7hl-lpae.config @@ -865,6 +865,9 @@ CONFIG_CHARGER_MAX8997=m # CONFIG_CHARGER_SBS is not set CONFIG_CHARGER_SMB347=m CONFIG_CHARGER_TPS65090=m +CONFIG_CHARLCD_BL_FLASH=y +# CONFIG_CHARLCD_BL_OFF is not set +# CONFIG_CHARLCD_BL_ON is not set # CONFIG_CHASH_SELFTEST is not set # CONFIG_CHASH_STATS is not set CONFIG_CHECKPOINT_RESTORE=y @@ -4126,6 +4129,7 @@ CONFIG_PACKET=y # CONFIG_PAGE_EXTENSION is not set # CONFIG_PAGE_OWNER is not set # CONFIG_PAGE_POISONING is not set +# CONFIG_PANEL_CHANGE_MESSAGE is not set # CONFIG_PANEL is not set # CONFIG_PANIC_ON_OOPS is not set CONFIG_PANIC_TIMEOUT=0 @@ -4135,6 +4139,7 @@ CONFIG_PARAVIRT=y # CONFIG_PARIDE is not set CONFIG_PARMAN=m # CONFIG_PARPORT is not set +# CONFIG_PARPORT_PANEL is not set # CONFIG_PARPORT_PC is not set CONFIG_PARTITION_ADVANCED=y # CONFIG_PATA_ALI is not set diff --git a/kernel-armv7hl.config b/kernel-armv7hl.config index 6b35cf491..753e1798c 100644 --- a/kernel-armv7hl.config +++ b/kernel-armv7hl.config @@ -894,6 +894,9 @@ CONFIG_CHARGER_SMB347=m CONFIG_CHARGER_TPS65090=m CONFIG_CHARGER_TPS65217=m CONFIG_CHARGER_TWL4030=m +CONFIG_CHARLCD_BL_FLASH=y +# CONFIG_CHARLCD_BL_OFF is not set +# CONFIG_CHARLCD_BL_ON is not set # CONFIG_CHASH_SELFTEST is not set # CONFIG_CHASH_STATS is not set CONFIG_CHECKPOINT_RESTORE=y @@ -4314,6 +4317,7 @@ CONFIG_PACKET=y # CONFIG_PAGE_OWNER is not set # CONFIG_PAGE_POISONING is not set CONFIG_PALMAS_GPADC=m +# CONFIG_PANEL_CHANGE_MESSAGE is not set # CONFIG_PANEL is not set # CONFIG_PANIC_ON_OOPS is not set CONFIG_PANIC_TIMEOUT=0 @@ -4323,6 +4327,7 @@ CONFIG_PARAVIRT=y # CONFIG_PARIDE is not set CONFIG_PARMAN=m # CONFIG_PARPORT is not set +# CONFIG_PARPORT_PANEL is not set # CONFIG_PARPORT_PC is not set CONFIG_PARTITION_ADVANCED=y # CONFIG_PATA_ALI is not set diff --git a/kernel-i686-debug.config b/kernel-i686-debug.config index 9634bf0f5..8be528172 100644 --- a/kernel-i686-debug.config +++ b/kernel-i686-debug.config @@ -736,6 +736,9 @@ CONFIG_CHARGER_CROS_USBPD=m # CONFIG_CHARGER_RT9455 is not set # CONFIG_CHARGER_SBS is not set CONFIG_CHARGER_SMB347=m +CONFIG_CHARLCD_BL_FLASH=y +# CONFIG_CHARLCD_BL_OFF is not set +# CONFIG_CHARLCD_BL_ON is not set # CONFIG_CHASH_SELFTEST is not set # CONFIG_CHASH_STATS is not set # CONFIG_CHECKPOINT_RESTORE is not set @@ -3926,6 +3929,7 @@ CONFIG_PACKET=y # CONFIG_PAGE_POISONING is not set CONFIG_PAGE_TABLE_ISOLATION=y CONFIG_PANASONIC_LAPTOP=m +# CONFIG_PANEL_CHANGE_MESSAGE is not set # CONFIG_PANEL is not set # CONFIG_PANIC_ON_OOPS is not set CONFIG_PANIC_TIMEOUT=0 @@ -3939,6 +3943,7 @@ CONFIG_PARMAN=m CONFIG_PARPORT_1284=y # CONFIG_PARPORT_AX88796 is not set CONFIG_PARPORT=m +# CONFIG_PARPORT_PANEL is not set # CONFIG_PARPORT_PC_FIFO is not set CONFIG_PARPORT_PC=m CONFIG_PARPORT_PC_PCMCIA=m diff --git a/kernel-i686.config b/kernel-i686.config index 9cb41e257..f1b01cec3 100644 --- a/kernel-i686.config +++ b/kernel-i686.config @@ -735,6 +735,9 @@ CONFIG_CHARGER_CROS_USBPD=m # CONFIG_CHARGER_RT9455 is not set # CONFIG_CHARGER_SBS is not set CONFIG_CHARGER_SMB347=m +CONFIG_CHARLCD_BL_FLASH=y +# CONFIG_CHARLCD_BL_OFF is not set +# CONFIG_CHARLCD_BL_ON is not set # CONFIG_CHASH_SELFTEST is not set # CONFIG_CHASH_STATS is not set # CONFIG_CHECKPOINT_RESTORE is not set @@ -3907,6 +3910,7 @@ CONFIG_PACKET=y # CONFIG_PAGE_POISONING is not set CONFIG_PAGE_TABLE_ISOLATION=y CONFIG_PANASONIC_LAPTOP=m +# CONFIG_PANEL_CHANGE_MESSAGE is not set # CONFIG_PANEL is not set # CONFIG_PANIC_ON_OOPS is not set CONFIG_PANIC_TIMEOUT=0 @@ -3920,6 +3924,7 @@ CONFIG_PARMAN=m CONFIG_PARPORT_1284=y # CONFIG_PARPORT_AX88796 is not set CONFIG_PARPORT=m +# CONFIG_PARPORT_PANEL is not set # CONFIG_PARPORT_PC_FIFO is not set CONFIG_PARPORT_PC=m CONFIG_PARPORT_PC_PCMCIA=m diff --git a/kernel-ppc64le-debug.config b/kernel-ppc64le-debug.config index 7169d3f08..40ab2f4ce 100644 --- a/kernel-ppc64le-debug.config +++ b/kernel-ppc64le-debug.config @@ -674,6 +674,9 @@ CONFIG_CGROUPS=y # CONFIG_CHARGER_RT9455 is not set # CONFIG_CHARGER_SBS is not set CONFIG_CHARGER_SMB347=m +CONFIG_CHARLCD_BL_FLASH=y +# CONFIG_CHARLCD_BL_OFF is not set +# CONFIG_CHARLCD_BL_ON is not set # CONFIG_CHASH_SELFTEST is not set # CONFIG_CHASH_STATS is not set CONFIG_CHECKPOINT_RESTORE=y @@ -3647,6 +3650,7 @@ CONFIG_PACKET=y # CONFIG_PAGE_EXTENSION is not set # CONFIG_PAGE_OWNER is not set # CONFIG_PAGE_POISONING is not set +# CONFIG_PANEL_CHANGE_MESSAGE is not set # CONFIG_PANEL is not set # CONFIG_PANIC_ON_OOPS is not set CONFIG_PANIC_TIMEOUT=0 @@ -3655,6 +3659,7 @@ CONFIG_PAPR_SCM=m # CONFIG_PARIDE is not set CONFIG_PARMAN=m # CONFIG_PARPORT is not set +# CONFIG_PARPORT_PANEL is not set # CONFIG_PARPORT_PC is not set CONFIG_PARTITION_ADVANCED=y CONFIG_PATA_ALI=m diff --git a/kernel-ppc64le.config b/kernel-ppc64le.config index a43dd1ce4..7b35f1d41 100644 --- a/kernel-ppc64le.config +++ b/kernel-ppc64le.config @@ -673,6 +673,9 @@ CONFIG_CGROUPS=y # CONFIG_CHARGER_RT9455 is not set # CONFIG_CHARGER_SBS is not set CONFIG_CHARGER_SMB347=m +CONFIG_CHARLCD_BL_FLASH=y +# CONFIG_CHARLCD_BL_OFF is not set +# CONFIG_CHARLCD_BL_ON is not set # CONFIG_CHASH_SELFTEST is not set # CONFIG_CHASH_STATS is not set CONFIG_CHECKPOINT_RESTORE=y @@ -3626,6 +3629,7 @@ CONFIG_PACKET=y # CONFIG_PAGE_EXTENSION is not set # CONFIG_PAGE_OWNER is not set # CONFIG_PAGE_POISONING is not set +# CONFIG_PANEL_CHANGE_MESSAGE is not set # CONFIG_PANEL is not set # CONFIG_PANIC_ON_OOPS is not set CONFIG_PANIC_TIMEOUT=0 @@ -3634,6 +3638,7 @@ CONFIG_PAPR_SCM=m # CONFIG_PARIDE is not set CONFIG_PARMAN=m # CONFIG_PARPORT is not set +# CONFIG_PARPORT_PANEL is not set # CONFIG_PARPORT_PC is not set CONFIG_PARTITION_ADVANCED=y CONFIG_PATA_ALI=m diff --git a/kernel-s390x-debug.config b/kernel-s390x-debug.config index 8d2e304f7..8eb57e9ec 100644 --- a/kernel-s390x-debug.config +++ b/kernel-s390x-debug.config @@ -681,6 +681,9 @@ CONFIG_CGROUPS=y # CONFIG_CHARGER_RT9455 is not set # CONFIG_CHARGER_SBS is not set # CONFIG_CHARGER_SMB347 is not set +CONFIG_CHARLCD_BL_FLASH=y +# CONFIG_CHARLCD_BL_OFF is not set +# CONFIG_CHARLCD_BL_ON is not set # CONFIG_CHASH_SELFTEST is not set # CONFIG_CHASH_STATS is not set CONFIG_CHECKPOINT_RESTORE=y @@ -3614,6 +3617,7 @@ CONFIG_PACK_STACK=y # CONFIG_PAGE_EXTENSION is not set # CONFIG_PAGE_OWNER is not set # CONFIG_PAGE_POISONING is not set +# CONFIG_PANEL_CHANGE_MESSAGE is not set # CONFIG_PANEL is not set # CONFIG_PANIC_ON_OOPS is not set CONFIG_PANIC_TIMEOUT=0 @@ -3621,6 +3625,7 @@ CONFIG_PANTHERLORD_FF=y # CONFIG_PARIDE is not set CONFIG_PARMAN=m # CONFIG_PARPORT is not set +# CONFIG_PARPORT_PANEL is not set # CONFIG_PARPORT_PC is not set CONFIG_PARTITION_ADVANCED=y CONFIG_PATA_ALI=m diff --git a/kernel-s390x.config b/kernel-s390x.config index a72714ceb..75ace4633 100644 --- a/kernel-s390x.config +++ b/kernel-s390x.config @@ -680,6 +680,9 @@ CONFIG_CGROUPS=y # CONFIG_CHARGER_RT9455 is not set # CONFIG_CHARGER_SBS is not set # CONFIG_CHARGER_SMB347 is not set +CONFIG_CHARLCD_BL_FLASH=y +# CONFIG_CHARLCD_BL_OFF is not set +# CONFIG_CHARLCD_BL_ON is not set # CONFIG_CHASH_SELFTEST is not set # CONFIG_CHASH_STATS is not set CONFIG_CHECKPOINT_RESTORE=y @@ -3593,6 +3596,7 @@ CONFIG_PACK_STACK=y # CONFIG_PAGE_EXTENSION is not set # CONFIG_PAGE_OWNER is not set # CONFIG_PAGE_POISONING is not set +# CONFIG_PANEL_CHANGE_MESSAGE is not set # CONFIG_PANEL is not set # CONFIG_PANIC_ON_OOPS is not set CONFIG_PANIC_TIMEOUT=0 @@ -3600,6 +3604,7 @@ CONFIG_PANTHERLORD_FF=y # CONFIG_PARIDE is not set CONFIG_PARMAN=m # CONFIG_PARPORT is not set +# CONFIG_PARPORT_PANEL is not set # CONFIG_PARPORT_PC is not set CONFIG_PARTITION_ADVANCED=y CONFIG_PATA_ALI=m diff --git a/kernel-x86_64-debug.config b/kernel-x86_64-debug.config index e173506d8..40a3afb1f 100644 --- a/kernel-x86_64-debug.config +++ b/kernel-x86_64-debug.config @@ -745,6 +745,9 @@ CONFIG_CHARGER_CROS_USBPD=m # CONFIG_CHARGER_RT9455 is not set # CONFIG_CHARGER_SBS is not set CONFIG_CHARGER_SMB347=m +CONFIG_CHARLCD_BL_FLASH=y +# CONFIG_CHARLCD_BL_OFF is not set +# CONFIG_CHARLCD_BL_ON is not set # CONFIG_CHASH_SELFTEST is not set # CONFIG_CHASH_STATS is not set CONFIG_CHECKPOINT_RESTORE=y @@ -3974,6 +3977,7 @@ CONFIG_PACKET=y # CONFIG_PAGE_POISONING is not set CONFIG_PAGE_TABLE_ISOLATION=y CONFIG_PANASONIC_LAPTOP=m +# CONFIG_PANEL_CHANGE_MESSAGE is not set # CONFIG_PANEL is not set # CONFIG_PANIC_ON_OOPS is not set CONFIG_PANIC_TIMEOUT=0 @@ -3987,6 +3991,7 @@ CONFIG_PARMAN=m CONFIG_PARPORT_1284=y # CONFIG_PARPORT_AX88796 is not set CONFIG_PARPORT=m +# CONFIG_PARPORT_PANEL is not set # CONFIG_PARPORT_PC_FIFO is not set CONFIG_PARPORT_PC=m CONFIG_PARPORT_PC_PCMCIA=m diff --git a/kernel-x86_64.config b/kernel-x86_64.config index 4f5460c49..0e13b05c8 100644 --- a/kernel-x86_64.config +++ b/kernel-x86_64.config @@ -744,6 +744,9 @@ CONFIG_CHARGER_CROS_USBPD=m # CONFIG_CHARGER_RT9455 is not set # CONFIG_CHARGER_SBS is not set CONFIG_CHARGER_SMB347=m +CONFIG_CHARLCD_BL_FLASH=y +# CONFIG_CHARLCD_BL_OFF is not set +# CONFIG_CHARLCD_BL_ON is not set # CONFIG_CHASH_SELFTEST is not set # CONFIG_CHASH_STATS is not set CONFIG_CHECKPOINT_RESTORE=y @@ -3955,6 +3958,7 @@ CONFIG_PACKET=y # CONFIG_PAGE_POISONING is not set CONFIG_PAGE_TABLE_ISOLATION=y CONFIG_PANASONIC_LAPTOP=m +# CONFIG_PANEL_CHANGE_MESSAGE is not set # CONFIG_PANEL is not set # CONFIG_PANIC_ON_OOPS is not set CONFIG_PANIC_TIMEOUT=0 @@ -3968,6 +3972,7 @@ CONFIG_PARMAN=m CONFIG_PARPORT_1284=y # CONFIG_PARPORT_AX88796 is not set CONFIG_PARPORT=m +# CONFIG_PARPORT_PANEL is not set # CONFIG_PARPORT_PC_FIFO is not set CONFIG_PARPORT_PC=m CONFIG_PARPORT_PC_PCMCIA=m diff --git a/kernel.spec b/kernel.spec index 4c20ee448..add029970 100644 --- a/kernel.spec +++ b/kernel.spec @@ -75,9 +75,9 @@ Summary: The Linux kernel # The next upstream release sublevel (base_sublevel+1) %define upstream_sublevel %(echo $((%{base_sublevel} + 1))) # The rc snapshot level -%global rcrev 1 +%global rcrev 2 # The git snapshot level -%define gitrev 2 +%define gitrev 0 # Set rpm version accordingly %define rpmversion 5.%{upstream_sublevel}.0 %endif @@ -585,6 +585,12 @@ Patch312: arm64-rock960-enable-tsadc.patch Patch339: bcm2835-cpufreq-add-CPU-frequency-control-driver.patch +# Tegra bits +Patch340: arm64-tegra-jetson-tx1-fixes.patch + +# https://patchwork.kernel.org/patch/10858639/ +Patch341: arm64-tegra-Add-NVIDIA-Jetson-Nano-Developer-Kit-support.patch + # 400 - IBM (ppc/s390x) patches # 500 - Temp fixes/CVEs etc @@ -599,6 +605,9 @@ Patch507: 0001-Drop-that-for-now.patch # rhbz 1689750, patch submitted upstream Patch508: 0001-virt-vbox-Implement-passing-requestor-info-to-the-ho.patch +# rhbz 1688283 +Patch512: v3-tpm-fix-an-invalid-condition-in-tpm_common_poll.patch + # END OF PATCH DEFINITIONS %endif @@ -1875,6 +1884,16 @@ fi # # %changelog +* Mon Mar 25 2019 Jeremy Cline <jcline@redhat.com> - 5.1.0-0.rc2.git0.1 +- Linux v5.1-rc2 + +* Mon Mar 25 2019 Jeremy Cline <jcline@redhat.com> +- Disable debugging options. + +* Sat Mar 23 2019 Peter Robinson <pbrobinson@fedoraproject.org> +- Fixes for Tegra Jetson TX series +- Initial support for NVIDIA Jetson Nano + * Fri Mar 22 2019 Jeremy Cline <jcline@redhat.com> - 5.1.0-0.rc1.git2.1 - Linux v5.1-rc1-66-gfd1f297b794c @@ -1,3 +1,2 @@ SHA512 (linux-5.0.tar.xz) = 3fbab70c7b03b1a10e9fa14d1e2e1f550faba4f5792b7699ca006951da74ab86e7d7f19c6a67849ab99343186e7d6f2752cd910d76222213b93c1eab90abf1b0 -SHA512 (patch-5.1-rc1.xz) = 013b5354de22870555cf604d756acb0ab90e4383c59e11671611a6dbd88de8cca4ca4727a428e5aa563b6aad66aad01539eee0d9adb594c58d18edffe3f2e82e -SHA512 (patch-5.1-rc1-git2.xz) = 1633b72619cfb2a20934d11f153ca32e22de75ebc4bef6c9baf2d2644237b1832bfdeec554d93d638fdb30609a0049a9cc0e9def49047793d4b12e8d90ff8c0f +SHA512 (patch-5.1-rc2.xz) = 97ea50f639b986b9cee8d44d01bddb25c92fd263322f9a22e4bdf06307f1a67ad9d345666928ba9a790b0f366bb012b748bd0e073999d4547e1cafc9ecdc770e diff --git a/v3-tpm-fix-an-invalid-condition-in-tpm_common_poll.patch b/v3-tpm-fix-an-invalid-condition-in-tpm_common_poll.patch new file mode 100644 index 000000000..606373aa4 --- /dev/null +++ b/v3-tpm-fix-an-invalid-condition-in-tpm_common_poll.patch @@ -0,0 +1,103 @@ +From patchwork Thu Mar 21 23:02:12 2019 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 8bit +X-Patchwork-Submitter: Tadeusz Struk <tadeusz.struk@intel.com> +X-Patchwork-Id: 10864497 +Return-Path: <linux-integrity-owner@kernel.org> +Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org + [172.30.200.125]) + by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 711816C2 + for <patchwork-linux-integrity@patchwork.kernel.org>; + Thu, 21 Mar 2019 23:02:15 +0000 (UTC) +Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) + by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 57B312A4A8 + for <patchwork-linux-integrity@patchwork.kernel.org>; + Thu, 21 Mar 2019 23:02:15 +0000 (UTC) +Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) + id 4AA482A539; Thu, 21 Mar 2019 23:02:15 +0000 (UTC) +X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on + pdx-wl-mail.web.codeaurora.org +X-Spam-Level: +X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, + RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 +Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) + by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C399A2A4A8 + for <patchwork-linux-integrity@patchwork.kernel.org>; + Thu, 21 Mar 2019 23:02:14 +0000 (UTC) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S1727157AbfCUXCO (ORCPT + <rfc822;patchwork-linux-integrity@patchwork.kernel.org>); + Thu, 21 Mar 2019 19:02:14 -0400 +Received: from mga04.intel.com ([192.55.52.120]:7149 "EHLO mga04.intel.com" + rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP + id S1727086AbfCUXCO (ORCPT <rfc822;linux-integrity@vger.kernel.org>); + Thu, 21 Mar 2019 19:02:14 -0400 +X-Amp-Result: SKIPPED(no attachment in message) +X-Amp-File-Uploaded: False +Received: from orsmga004.jf.intel.com ([10.7.209.38]) + by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; + 21 Mar 2019 16:02:13 -0700 +X-ExtLoop1: 1 +X-IronPort-AV: E=Sophos;i="5.60,254,1549958400"; + d="scan'208";a="284777192" +Received: from jdemuth-mobl.amr.corp.intel.com (HELO + tstruk-mobl1.jf.intel.com) ([10.251.150.110]) + by orsmga004.jf.intel.com with ESMTP; 21 Mar 2019 16:02:13 -0700 +Subject: [PATCH v3] tpm: fix an invalid condition in tpm_common_poll +From: Tadeusz Struk <tadeusz.struk@intel.com> +To: jarkko.sakkinen@linux.intel.com +Cc: grawity@gmail.com, James.Bottomley@HansenPartnership.com, + linux-integrity@vger.kernel.org, linux-kernel@vger.kernel.org, + stable@vger.kernel.org, tadeusz.struk@intel.com +Date: Thu, 21 Mar 2019 16:02:12 -0700 +Message-ID: + <155320933278.5015.1752135965699928631.stgit@tstruk-mobl1.jf.intel.com> +User-Agent: StGit/unknown-version +MIME-Version: 1.0 +Content-Type: text/plain; charset="utf-8" +Sender: linux-integrity-owner@vger.kernel.org +Precedence: bulk +List-ID: <linux-integrity.vger.kernel.org> +X-Mailing-List: linux-integrity@vger.kernel.org +X-Virus-Scanned: ClamAV using ClamSMTP + +The poll condition should only check response_length, +because reads should only be issued if there is data to read. +The response_read flag only prevents double writes. +The problem was that the write set the response_read to false, +enqued a tpm job, and returned. Then application called poll +which checked the response_read flag and returned EPOLLIN. +Then the application called read, but got nothing. +After all that the async_work kicked in. +Added also mutex_lock around the poll check to prevent +other possible race conditions. + +Fixes: 9488585b21bef0df12 ("tpm: add support for partial reads") +Reported-by: Mantas Mikulėnas <grawity@gmail.com> +Tested-by: Mantas Mikulėnas <grawity@gmail.com> +Signed-off-by: Tadeusz Struk <tadeusz.struk@intel.com> +--- + drivers/char/tpm/tpm-dev-common.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/drivers/char/tpm/tpm-dev-common.c b/drivers/char/tpm/tpm-dev-common.c +index 5eecad233ea1..7312d3214381 100644 +--- a/drivers/char/tpm/tpm-dev-common.c ++++ b/drivers/char/tpm/tpm-dev-common.c +@@ -203,12 +203,14 @@ __poll_t tpm_common_poll(struct file *file, poll_table *wait) + __poll_t mask = 0; + + poll_wait(file, &priv->async_wait, wait); ++ mutex_lock(&priv->buffer_mutex); + +- if (!priv->response_read || priv->response_length) ++ if (priv->response_length) + mask = EPOLLIN | EPOLLRDNORM; + else + mask = EPOLLOUT | EPOLLWRNORM; + ++ mutex_unlock(&priv->buffer_mutex); + return mask; + } + |