diff options
| -rw-r--r-- | 0001-ALSA-seq-Fix-use-after-free-at-creating-a-port.patch | 140 | ||||
| -rw-r--r-- | arm-exynos-fix-usb3.patch | 411 | ||||
| -rw-r--r-- | arm64-aw64-devices.patch | 712 | ||||
| -rw-r--r-- | baseconfig/arm/CONFIG_SUNXI_SRAM (renamed from baseconfig/arm/armv7/CONFIG_SUNXI_SRAM) | 0 | ||||
| -rw-r--r-- | kernel-aarch64-debug.config | 1 | ||||
| -rw-r--r-- | kernel-aarch64.config | 1 | ||||
| -rw-r--r-- | kernel.spec | 17 | ||||
| -rw-r--r-- | sources | 2 |
8 files changed, 1281 insertions, 3 deletions
diff --git a/0001-ALSA-seq-Fix-use-after-free-at-creating-a-port.patch b/0001-ALSA-seq-Fix-use-after-free-at-creating-a-port.patch new file mode 100644 index 000000000..d04add8aa --- /dev/null +++ b/0001-ALSA-seq-Fix-use-after-free-at-creating-a-port.patch @@ -0,0 +1,140 @@ +From 71105998845fb012937332fe2e806d443c09e026 Mon Sep 17 00:00:00 2001 +From: Takashi Iwai <tiwai@suse.de> +Date: Mon, 9 Oct 2017 11:09:20 +0200 +Subject: [PATCH] ALSA: seq: Fix use-after-free at creating a port + +There is a potential race window opened at creating and deleting a +port via ioctl, as spotted by fuzzing. snd_seq_create_port() creates +a port object and returns its pointer, but it doesn't take the +refcount, thus it can be deleted immediately by another thread. +Meanwhile, snd_seq_ioctl_create_port() still calls the function +snd_seq_system_client_ev_port_start() with the created port object +that is being deleted, and this triggers use-after-free like: + + BUG: KASAN: use-after-free in snd_seq_ioctl_create_port+0x504/0x630 [snd_seq] at addr ffff8801f2241cb1 + ============================================================================= + BUG kmalloc-512 (Tainted: G B ): kasan: bad access detected + ----------------------------------------------------------------------------- + INFO: Allocated in snd_seq_create_port+0x94/0x9b0 [snd_seq] age=1 cpu=3 pid=4511 + ___slab_alloc+0x425/0x460 + __slab_alloc+0x20/0x40 + kmem_cache_alloc_trace+0x150/0x190 + snd_seq_create_port+0x94/0x9b0 [snd_seq] + snd_seq_ioctl_create_port+0xd1/0x630 [snd_seq] + snd_seq_do_ioctl+0x11c/0x190 [snd_seq] + snd_seq_ioctl+0x40/0x80 [snd_seq] + do_vfs_ioctl+0x54b/0xda0 + SyS_ioctl+0x79/0x90 + entry_SYSCALL_64_fastpath+0x16/0x75 + INFO: Freed in port_delete+0x136/0x1a0 [snd_seq] age=1 cpu=2 pid=4717 + __slab_free+0x204/0x310 + kfree+0x15f/0x180 + port_delete+0x136/0x1a0 [snd_seq] + snd_seq_delete_port+0x235/0x350 [snd_seq] + snd_seq_ioctl_delete_port+0xc8/0x180 [snd_seq] + snd_seq_do_ioctl+0x11c/0x190 [snd_seq] + snd_seq_ioctl+0x40/0x80 [snd_seq] + do_vfs_ioctl+0x54b/0xda0 + SyS_ioctl+0x79/0x90 + entry_SYSCALL_64_fastpath+0x16/0x75 + Call Trace: + [<ffffffff81b03781>] dump_stack+0x63/0x82 + [<ffffffff81531b3b>] print_trailer+0xfb/0x160 + [<ffffffff81536db4>] object_err+0x34/0x40 + [<ffffffff815392d3>] kasan_report.part.2+0x223/0x520 + [<ffffffffa07aadf4>] ? snd_seq_ioctl_create_port+0x504/0x630 [snd_seq] + [<ffffffff815395fe>] __asan_report_load1_noabort+0x2e/0x30 + [<ffffffffa07aadf4>] snd_seq_ioctl_create_port+0x504/0x630 [snd_seq] + [<ffffffffa07aa8f0>] ? snd_seq_ioctl_delete_port+0x180/0x180 [snd_seq] + [<ffffffff8136be50>] ? taskstats_exit+0xbc0/0xbc0 + [<ffffffffa07abc5c>] snd_seq_do_ioctl+0x11c/0x190 [snd_seq] + [<ffffffffa07abd10>] snd_seq_ioctl+0x40/0x80 [snd_seq] + [<ffffffff8136d433>] ? acct_account_cputime+0x63/0x80 + [<ffffffff815b515b>] do_vfs_ioctl+0x54b/0xda0 + ..... + +We may fix this in a few different ways, and in this patch, it's fixed +simply by taking the refcount properly at snd_seq_create_port() and +letting the caller unref the object after use. Also, there is another +potential use-after-free by sprintf() call in snd_seq_create_port(), +and this is moved inside the lock. + +This fix covers CVE-2017-15265. + +Reported-and-tested-by: Michael23 Yu <ycqzsy@gmail.com> +Suggested-by: Linus Torvalds <torvalds@linux-foundation.org> +Cc: <stable@vger.kernel.org> +Signed-off-by: Takashi Iwai <tiwai@suse.de> +--- + sound/core/seq/seq_clientmgr.c | 6 +++++- + sound/core/seq/seq_ports.c | 7 +++++-- + 2 files changed, 10 insertions(+), 3 deletions(-) + +diff --git a/sound/core/seq/seq_clientmgr.c b/sound/core/seq/seq_clientmgr.c +index ea2d0ae85bd3..6c9cba2166d9 100644 +--- a/sound/core/seq/seq_clientmgr.c ++++ b/sound/core/seq/seq_clientmgr.c +@@ -1259,6 +1259,7 @@ static int snd_seq_ioctl_create_port(struct snd_seq_client *client, void *arg) + struct snd_seq_port_info *info = arg; + struct snd_seq_client_port *port; + struct snd_seq_port_callback *callback; ++ int port_idx; + + /* it is not allowed to create the port for an another client */ + if (info->addr.client != client->number) +@@ -1269,7 +1270,9 @@ static int snd_seq_ioctl_create_port(struct snd_seq_client *client, void *arg) + return -ENOMEM; + + if (client->type == USER_CLIENT && info->kernel) { +- snd_seq_delete_port(client, port->addr.port); ++ port_idx = port->addr.port; ++ snd_seq_port_unlock(port); ++ snd_seq_delete_port(client, port_idx); + return -EINVAL; + } + if (client->type == KERNEL_CLIENT) { +@@ -1290,6 +1293,7 @@ static int snd_seq_ioctl_create_port(struct snd_seq_client *client, void *arg) + + snd_seq_set_port_info(port, info); + snd_seq_system_client_ev_port_start(port->addr.client, port->addr.port); ++ snd_seq_port_unlock(port); + + return 0; + } +diff --git a/sound/core/seq/seq_ports.c b/sound/core/seq/seq_ports.c +index 0a7020c82bfc..d21ece9f8d73 100644 +--- a/sound/core/seq/seq_ports.c ++++ b/sound/core/seq/seq_ports.c +@@ -122,7 +122,9 @@ static void port_subs_info_init(struct snd_seq_port_subs_info *grp) + } + + +-/* create a port, port number is returned (-1 on failure) */ ++/* create a port, port number is returned (-1 on failure); ++ * the caller needs to unref the port via snd_seq_port_unlock() appropriately ++ */ + struct snd_seq_client_port *snd_seq_create_port(struct snd_seq_client *client, + int port) + { +@@ -151,6 +153,7 @@ struct snd_seq_client_port *snd_seq_create_port(struct snd_seq_client *client, + snd_use_lock_init(&new_port->use_lock); + port_subs_info_init(&new_port->c_src); + port_subs_info_init(&new_port->c_dest); ++ snd_use_lock_use(&new_port->use_lock); + + num = port >= 0 ? port : 0; + mutex_lock(&client->ports_mutex); +@@ -165,9 +168,9 @@ struct snd_seq_client_port *snd_seq_create_port(struct snd_seq_client *client, + list_add_tail(&new_port->list, &p->list); + client->num_ports++; + new_port->addr.port = num; /* store the port number in the port */ ++ sprintf(new_port->name, "port-%d", num); + write_unlock_irqrestore(&client->ports_lock, flags); + mutex_unlock(&client->ports_mutex); +- sprintf(new_port->name, "port-%d", num); + + return new_port; + } +-- +2.13.5 + diff --git a/arm-exynos-fix-usb3.patch b/arm-exynos-fix-usb3.patch new file mode 100644 index 000000000..cb5828acf --- /dev/null +++ b/arm-exynos-fix-usb3.patch @@ -0,0 +1,411 @@ +From patchwork Mon Oct 9 12:00:50 2017 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [PATCHv4,1/2] drivers: phy: add calibrate method +From: Andrzej Pietrasiewicz <andrzej.p@samsung.com> +X-Patchwork-Id: 9992829 +Message-Id: <1507550451-21324-2-git-send-email-andrzej.p@samsung.com> +To: linux-samsung-soc@vger.kernel.org, linux-usb@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org +Cc: Mark Rutland <mark.rutland@arm.com>, Felipe Balbi <balbi@kernel.org>, + Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>, + Greg Kroah-Hartman <gregkh@linuxfoundation.org>, + Russell King <linux@armlinux.org.uk>, + Krzysztof Kozlowski <krzk@kernel.org>, + Kishon Vijay Abraham I <kishon@ti.com>, + Rob Herring <robh+dt@kernel.org>, Kukjin Kim <kgene@kernel.org>, + Andrzej Pietrasiewicz <andrzej.p@samsung.com>, + Marek Szyprowski <m.szyprowski@samsung.com> +Date: Mon, 09 Oct 2017 14:00:50 +0200 + +Some quirky UDCs (like dwc3 on Exynos) need to have their phys calibrated e.g. +for using super speed. This patch adds a new phy_calibrate() method. +When the calibration should be used is dependent on actual chip. + +In case of dwc3 on Exynos the calibration must happen after usb_add_hcd() +(while in host mode), because certain phy parameters like Tx LOS levels +and boost levels need to be calibrated further post initialization of xHCI +controller, to get SuperSpeed operations working. But an hcd must be +prepared first in order to pass it to usb_add_hcd(), so, in particular, dwc3 +registers must be available first, and in order for the latter to happen +the phys must be initialized. This poses a chicken and egg problem if +the calibration were to be performed in phy_init(). To break the circular +dependency a separate method is added which can be called at a desired +moment after phy intialization. + +Signed-off-by: Andrzej Pietrasiewicz <andrzej.p@samsung.com> +--- + drivers/phy/phy-core.c | 15 +++++++++++++++ + include/linux/phy/phy.h | 10 ++++++++++ + 2 files changed, 25 insertions(+) + +diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c +index a268f4d..b4964b0 100644 +--- a/drivers/phy/phy-core.c ++++ b/drivers/phy/phy-core.c +@@ -372,6 +372,21 @@ int phy_reset(struct phy *phy) + } + EXPORT_SYMBOL_GPL(phy_reset); + ++int phy_calibrate(struct phy *phy) ++{ ++ int ret; ++ ++ if (!phy || !phy->ops->calibrate) ++ return 0; ++ ++ mutex_lock(&phy->mutex); ++ ret = phy->ops->calibrate(phy); ++ mutex_unlock(&phy->mutex); ++ ++ return ret; ++} ++EXPORT_SYMBOL_GPL(phy_calibrate); ++ + /** + * _of_phy_get() - lookup and obtain a reference to a phy by phandle + * @np: device_node for which to get the phy +diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h +index e694d40..87580c8 100644 +--- a/include/linux/phy/phy.h ++++ b/include/linux/phy/phy.h +@@ -39,6 +39,7 @@ enum phy_mode { + * @power_off: powering off the phy + * @set_mode: set the mode of the phy + * @reset: resetting the phy ++ * @calibrate: calibrate the phy + * @owner: the module owner containing the ops + */ + struct phy_ops { +@@ -48,6 +49,7 @@ struct phy_ops { + int (*power_off)(struct phy *phy); + int (*set_mode)(struct phy *phy, enum phy_mode mode); + int (*reset)(struct phy *phy); ++ int (*calibrate)(struct phy *phy); + struct module *owner; + }; + +@@ -141,6 +143,7 @@ static inline void *phy_get_drvdata(struct phy *phy) + int phy_power_off(struct phy *phy); + int phy_set_mode(struct phy *phy, enum phy_mode mode); + int phy_reset(struct phy *phy); ++int phy_calibrate(struct phy *phy); + static inline int phy_get_bus_width(struct phy *phy) + { + return phy->attrs.bus_width; +@@ -262,6 +265,13 @@ static inline int phy_reset(struct phy *phy) + return -ENOSYS; + } + ++static inline int phy_calibrate(struct phy *phy) ++{ ++ if (!phy) ++ return 0; ++ return -ENOSYS; ++} ++ + static inline int phy_get_bus_width(struct phy *phy) + { + return -ENOSYS; +From patchwork Mon Oct 9 12:00:51 2017 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [PATCHv4, + 2/2] phy: exynos5-usbdrd: Calibrate LOS levels for exynos5420/5800 +From: Andrzej Pietrasiewicz <andrzej.p@samsung.com> +X-Patchwork-Id: 9992809 +Message-Id: <1507550451-21324-3-git-send-email-andrzej.p@samsung.com> +To: linux-samsung-soc@vger.kernel.org, linux-usb@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org +Cc: Mark Rutland <mark.rutland@arm.com>, Felipe Balbi <balbi@kernel.org>, + Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>, + Greg Kroah-Hartman <gregkh@linuxfoundation.org>, + Russell King <linux@armlinux.org.uk>, + Krzysztof Kozlowski <krzk@kernel.org>, + Kishon Vijay Abraham I <kishon@ti.com>, + Rob Herring <robh+dt@kernel.org>, Kukjin Kim <kgene@kernel.org>, + Andrzej Pietrasiewicz <andrzej.p@samsung.com>, + Marek Szyprowski <m.szyprowski@samsung.com> +Date: Mon, 09 Oct 2017 14:00:51 +0200 + +From: Vivek Gautam <gautam.vivek@samsung.com> + +Adding phy calibration sequence for USB 3.0 DRD PHY present on +Exynos5420/5800 systems. +This calibration facilitates setting certain PHY parameters viz. +the Loss-of-Signal (LOS) Detector Threshold Level, as well as +Tx-Vboost-Level for Super-Speed operations. +Additionally we also set proper time to wait for RxDetect measurement, +for desired PHY reference clock, so as to solve issue with enumeration +of few USB 3.0 devices, like Samsung SUM-TSB16S 3.0 USB drive +on the controller. + +We are using CR_port for this purpose to send required data +to override the LOS values. + +On testing with USB 3.0 devices on USB 3.0 port present on +SMDK5420, and peach-pit boards should see following message: +usb 2-1: new SuperSpeed USB device number 2 using xhci-hcd + +and without this patch, should see below shown message: +usb 1-1: new high-speed USB device number 2 using xhci-hcd + +[Also removed unnecessary extra lines in the register macro definitions] + +Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> +[adapted to use phy_calibrate as entry point] +Signed-off-by: Andrzej Pietrasiewicz <andrzej.p@samsung.com> +--- + drivers/phy/samsung/phy-exynos5-usbdrd.c | 183 +++++++++++++++++++++++++++++++ + drivers/usb/dwc3/core.c | 7 +- + 2 files changed, 188 insertions(+), 2 deletions(-) + +diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c +index 22c68f5..9e83c15 100644 +--- a/drivers/phy/samsung/phy-exynos5-usbdrd.c ++++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c +@@ -90,7 +90,17 @@ + #define PHYCLKRST_COMMONONN BIT(0) + + #define EXYNOS5_DRD_PHYREG0 0x14 ++#define PHYREG0_SSC_REF_CLK_SEL BIT(21) ++#define PHYREG0_SSC_RANGE BIT(20) ++#define PHYREG0_CR_WRITE BIT(19) ++#define PHYREG0_CR_READ BIT(18) ++#define PHYREG0_CR_DATA_IN(_x) ((_x) << 2) ++#define PHYREG0_CR_CAP_DATA BIT(1) ++#define PHYREG0_CR_CAP_ADDR BIT(0) ++ + #define EXYNOS5_DRD_PHYREG1 0x18 ++#define PHYREG1_CR_DATA_OUT(_x) ((_x) << 1) ++#define PHYREG1_CR_ACK BIT(0) + + #define EXYNOS5_DRD_PHYPARAM0 0x1c + +@@ -119,6 +129,25 @@ + #define EXYNOS5_DRD_PHYRESUME 0x34 + #define EXYNOS5_DRD_LINKPORT 0x44 + ++/* USB 3.0 DRD PHY SS Function Control Reg; accessed by CR_PORT */ ++#define EXYNOS5_DRD_PHYSS_LOSLEVEL_OVRD_IN (0x15) ++#define LOSLEVEL_OVRD_IN_LOS_BIAS_5420 (0x5 << 13) ++#define LOSLEVEL_OVRD_IN_LOS_BIAS_DEFAULT (0x0 << 13) ++#define LOSLEVEL_OVRD_IN_EN (0x1 << 10) ++#define LOSLEVEL_OVRD_IN_LOS_LEVEL_DEFAULT (0x9 << 0) ++ ++#define EXYNOS5_DRD_PHYSS_TX_VBOOSTLEVEL_OVRD_IN (0x12) ++#define TX_VBOOSTLEVEL_OVRD_IN_VBOOST_5420 (0x5 << 13) ++#define TX_VBOOSTLEVEL_OVRD_IN_VBOOST_DEFAULT (0x4 << 13) ++ ++#define EXYNOS5_DRD_PHYSS_LANE0_TX_DEBUG (0x1010) ++#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_19M2_20M (0x4 << 4) ++#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_24M (0x8 << 4) ++#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_25M_26M (0x8 << 4) ++#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_48M_50M_52M (0x20 << 4) ++#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_62M5 (0x20 << 4) ++#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_96M_100M (0x40 << 4) ++ + #define KHZ 1000 + #define MHZ (KHZ * KHZ) + +@@ -527,6 +556,151 @@ static int exynos5_usbdrd_phy_power_off(struct phy *phy) + return 0; + } + ++static int crport_handshake(struct exynos5_usbdrd_phy *phy_drd, ++ u32 val, u32 cmd) ++{ ++ u32 usec = 100; ++ unsigned int result; ++ ++ writel(val | cmd, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0); ++ ++ do { ++ result = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYREG1); ++ if (result & PHYREG1_CR_ACK) ++ break; ++ ++ udelay(1); ++ } while (usec-- > 0); ++ ++ if (!usec) { ++ dev_err(phy_drd->dev, ++ "CRPORT handshake timeout1 (0x%08x)\n", val); ++ return -ETIME; ++ } ++ ++ usec = 100; ++ ++ writel(val, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0); ++ ++ do { ++ result = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYREG1); ++ if (!(result & PHYREG1_CR_ACK)) ++ break; ++ ++ udelay(1); ++ } while (usec-- > 0); ++ ++ if (!usec) { ++ dev_err(phy_drd->dev, ++ "CRPORT handshake timeout2 (0x%08x)\n", val); ++ return -ETIME; ++ } ++ ++ return 0; ++} ++ ++static int crport_ctrl_write(struct exynos5_usbdrd_phy *phy_drd, ++ u32 addr, u32 data) ++{ ++ int ret; ++ ++ /* Write Address */ ++ writel(PHYREG0_CR_DATA_IN(addr), ++ phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0); ++ ret = crport_handshake(phy_drd, PHYREG0_CR_DATA_IN(addr), ++ PHYREG0_CR_CAP_ADDR); ++ if (ret) ++ return ret; ++ ++ /* Write Data */ ++ writel(PHYREG0_CR_DATA_IN(data), ++ phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0); ++ ret = crport_handshake(phy_drd, PHYREG0_CR_DATA_IN(data), ++ PHYREG0_CR_CAP_DATA); ++ if (ret) ++ return ret; ++ ++ ret = crport_handshake(phy_drd, PHYREG0_CR_DATA_IN(data), ++ PHYREG0_CR_WRITE); ++ ++ return ret; ++} ++ ++/* ++ * Calibrate few PHY parameters using CR_PORT register to meet ++ * SuperSpeed requirements on Exynos5420 and Exynos5800 systems, ++ * which have 28nm USB 3.0 DRD PHY. ++ */ ++static int exynos5420_usbdrd_phy_calibrate(struct exynos5_usbdrd_phy *phy_drd) ++{ ++ unsigned int temp; ++ int ret = 0; ++ ++ /* ++ * Change los_bias to (0x5) for 28nm PHY from a ++ * default value (0x0); los_level is set as default ++ * (0x9) as also reflected in los_level[30:26] bits ++ * of PHYPARAM0 register. ++ */ ++ temp = LOSLEVEL_OVRD_IN_LOS_BIAS_5420 | ++ LOSLEVEL_OVRD_IN_EN | ++ LOSLEVEL_OVRD_IN_LOS_LEVEL_DEFAULT; ++ ret = crport_ctrl_write(phy_drd, ++ EXYNOS5_DRD_PHYSS_LOSLEVEL_OVRD_IN, ++ temp); ++ if (ret) { ++ dev_err(phy_drd->dev, ++ "Failed setting Loss-of-Signal level for SuperSpeed\n"); ++ return ret; ++ } ++ ++ /* ++ * Set tx_vboost_lvl to (0x5) for 28nm PHY Tuning, ++ * to raise Tx signal level from its default value of (0x4) ++ */ ++ temp = TX_VBOOSTLEVEL_OVRD_IN_VBOOST_5420; ++ ret = crport_ctrl_write(phy_drd, ++ EXYNOS5_DRD_PHYSS_TX_VBOOSTLEVEL_OVRD_IN, ++ temp); ++ if (ret) { ++ dev_err(phy_drd->dev, ++ "Failed setting Tx-Vboost-Level for SuperSpeed\n"); ++ return ret; ++ } ++ ++ /* ++ * Set proper time to wait for RxDetect measurement, for ++ * desired reference clock of PHY, by tuning the CR_PORT ++ * register LANE0.TX_DEBUG which is internal to PHY. ++ * This fixes issue with few USB 3.0 devices, which are ++ * not detected (not even generate interrupts on the bus ++ * on insertion) without this change. ++ * e.g. Samsung SUM-TSB16S 3.0 USB drive. ++ */ ++ switch (phy_drd->extrefclk) { ++ case EXYNOS5_FSEL_50MHZ: ++ temp = LANE0_TX_DEBUG_RXDET_MEAS_TIME_48M_50M_52M; ++ break; ++ case EXYNOS5_FSEL_20MHZ: ++ case EXYNOS5_FSEL_19MHZ2: ++ temp = LANE0_TX_DEBUG_RXDET_MEAS_TIME_19M2_20M; ++ break; ++ case EXYNOS5_FSEL_24MHZ: ++ default: ++ temp = LANE0_TX_DEBUG_RXDET_MEAS_TIME_24M; ++ break; ++ } ++ ++ ret = crport_ctrl_write(phy_drd, ++ EXYNOS5_DRD_PHYSS_LANE0_TX_DEBUG, ++ temp); ++ if (ret) ++ dev_err(phy_drd->dev, ++ "Failed setting RxDetect measurement time for SuperSpeed\n"); ++ ++ return ret; ++} ++ + static struct phy *exynos5_usbdrd_phy_xlate(struct device *dev, + struct of_phandle_args *args) + { +@@ -538,11 +712,20 @@ static struct phy *exynos5_usbdrd_phy_xlate(struct device *dev, + return phy_drd->phys[args->args[0]].phy; + } + ++static int exynos5_usbdrd_phy_calibrate(struct phy *phy) ++{ ++ struct phy_usb_instance *inst = phy_get_drvdata(phy); ++ struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst); ++ ++ return exynos5420_usbdrd_phy_calibrate(phy_drd); ++} ++ + static const struct phy_ops exynos5_usbdrd_phy_ops = { + .init = exynos5_usbdrd_phy_init, + .exit = exynos5_usbdrd_phy_exit, + .power_on = exynos5_usbdrd_phy_power_on, + .power_off = exynos5_usbdrd_phy_power_off, ++ .calibrate = exynos5_usbdrd_phy_calibrate, + .owner = THIS_MODULE, + }; + +diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c +index 03474d3..224e0dd 100644 +--- a/drivers/usb/dwc3/core.c ++++ b/drivers/usb/dwc3/core.c +@@ -156,9 +156,10 @@ static void __dwc3_set_mode(struct work_struct *work) + } else { + if (dwc->usb2_phy) + otg_set_vbus(dwc->usb2_phy->otg, true); +- if (dwc->usb2_generic_phy) ++ if (dwc->usb2_generic_phy) { + phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); +- ++ phy_calibrate(dwc->usb2_generic_phy); ++ } + } + break; + case DWC3_GCTL_PRTCAP_DEVICE: +@@ -955,6 +956,8 @@ static int dwc3_core_init_mode(struct dwc3 *dwc) + dev_err(dev, "failed to initialize host\n"); + return ret; + } ++ if (dwc->usb2_generic_phy) ++ phy_calibrate(dwc->usb2_generic_phy); + break; + case USB_DR_MODE_OTG: + INIT_WORK(&dwc->drd_work, __dwc3_set_mode); diff --git a/arm64-aw64-devices.patch b/arm64-aw64-devices.patch new file mode 100644 index 000000000..94b1b2b04 --- /dev/null +++ b/arm64-aw64-devices.patch @@ -0,0 +1,712 @@ +From 4c0a84757b5a0365a5dde82e732972eda80a32b1 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng <icenowy@aosc.io> +Date: Thu, 18 May 2017 15:16:51 +0800 +Subject: arm64: allwinner: a64: add DTSI file for AXP803 PMIC + +As nearly all A64 boards are using AXP803 PMIC, add a DTSI file for it, +like the old DTSI files for AXP20x/22x, for the common parts of the +PMIC. + +Signed-off-by: Icenowy Zheng <icenowy@aosc.io> +Acked-by: Mark Brown <broonie@kernel.org> +Signed-off-by: Chen-Yu Tsai <wens@csie.org> +--- + arch/arm64/boot/dts/allwinner/axp803.dtsi | 150 ++++++++++++++++++++++++++++++ + 1 file changed, 150 insertions(+) + create mode 100644 arch/arm64/boot/dts/allwinner/axp803.dtsi + +diff --git a/arch/arm64/boot/dts/allwinner/axp803.dtsi b/arch/arm64/boot/dts/allwinner/axp803.dtsi +new file mode 100644 +index 0000000..ff8af52 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/axp803.dtsi +@@ -0,0 +1,150 @@ ++/* ++ * Copyright 2017 Icenowy Zheng <icenowy@aosc.xyz> ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This file is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This file is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/* ++ * AXP803 Integrated Power Management Chip ++ * http://files.pine64.org/doc/datasheet/pine64/AXP803_Datasheet_V1.0.pdf ++ */ ++ ++&axp803 { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ ++ regulators { ++ /* Default work frequency for buck regulators */ ++ x-powers,dcdc-freq = <3000>; ++ ++ reg_aldo1: aldo1 { ++ regulator-name = "aldo1"; ++ }; ++ ++ reg_aldo2: aldo2 { ++ regulator-name = "aldo2"; ++ }; ++ ++ reg_aldo3: aldo3 { ++ regulator-name = "aldo3"; ++ }; ++ ++ reg_dc1sw: dc1sw { ++ regulator-name = "dc1sw"; ++ }; ++ ++ reg_dcdc1: dcdc1 { ++ regulator-name = "dcdc1"; ++ }; ++ ++ reg_dcdc2: dcdc2 { ++ regulator-name = "dcdc2"; ++ }; ++ ++ reg_dcdc3: dcdc3 { ++ regulator-name = "dcdc3"; ++ }; ++ ++ reg_dcdc4: dcdc4 { ++ regulator-name = "dcdc4"; ++ }; ++ ++ reg_dcdc5: dcdc5 { ++ regulator-name = "dcdc5"; ++ }; ++ ++ reg_dcdc6: dcdc6 { ++ regulator-name = "dcdc6"; ++ }; ++ ++ reg_dldo1: dldo1 { ++ regulator-name = "dldo1"; ++ }; ++ ++ reg_dldo2: dldo2 { ++ regulator-name = "dldo2"; ++ }; ++ ++ reg_dldo3: dldo3 { ++ regulator-name = "dldo3"; ++ }; ++ ++ reg_dldo4: dldo4 { ++ regulator-name = "dldo4"; ++ }; ++ ++ reg_eldo1: eldo1 { ++ regulator-name = "eldo1"; ++ }; ++ ++ reg_eldo2: eldo2 { ++ regulator-name = "eldo2"; ++ }; ++ ++ reg_eldo3: eldo3 { ++ regulator-name = "eldo3"; ++ }; ++ ++ reg_fldo1: fldo1 { ++ regulator-name = "fldo1"; ++ }; ++ ++ reg_fldo2: fldo2 { ++ regulator-name = "fldo2"; ++ }; ++ ++ reg_ldo_io0: ldo-io0 { ++ regulator-name = "ldo-io0"; ++ status = "disabled"; ++ }; ++ ++ reg_ldo_io1: ldo-io1 { ++ regulator-name = "ldo-io1"; ++ status = "disabled"; ++ }; ++ ++ reg_rtc_ldo: rtc-ldo { ++ /* RTC_LDO is a fixed, always-on regulator */ ++ regulator-always-on; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-name = "rtc-ldo"; ++ }; ++ }; ++}; +-- +cgit v1.1 +From 535ca50858e2d8bf1618ace056cd96f0b3d01133 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng <icenowy@aosc.io> +Date: Tue, 6 Jun 2017 13:59:32 +0800 +Subject: arm64: allwinner: a64: add NMI (R_INTC) controller on A64 + +Allwinner A64 SoC features a R_INTC controller, which controls the NMI +line, and this interrupt line is usually connected to the AXP PMIC. + +Add support for it. + +Signed-off-by: Icenowy Zheng <icenowy@aosc.io> +[wens@csie.org: Add fallback sun6i-a31-r-intc compatible] +Signed-off-by: Chen-Yu Tsai <wens@csie.org> +Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> +--- + arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +index 9d00622..78c7c9d 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +@@ -487,6 +487,15 @@ + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + }; + ++ r_intc: interrupt-controller@1f00c00 { ++ compatible = "allwinner,sun50i-a64-r-intc", ++ "allwinner,sun6i-a31-r-intc"; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ reg = <0x01f00c00 0x400>; ++ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; ++ }; ++ + r_ccu: clock@1f01400 { + compatible = "allwinner,sun50i-a64-r-ccu"; + reg = <0x01f01400 0x100>; +-- +cgit v1.1 +From bf397214530ee5c873dac7b12126b250afd3831f Mon Sep 17 00:00:00 2001 +From: Jagan Teki <jagan@amarulasolutions.com> +Date: Mon, 14 Aug 2017 16:06:53 +0530 +Subject: arm64: allwinner: a64: Add initial NanoPi A64 support + +NanoPi A64 is a new board of high performance with low cost +designed by FriendlyElec., using the Allwinner A64 SOC. + +Nanopi A64 features +- Allwinner A64, 64-bit Quad-core Cortex-A53@648MHz to 1.152GHz, DVFS +- 1GB DDR3 RAM +- MicroSD +- Gigabit Ethernet (RTL8211E) +- Wi-Fi 802.11b/g/n +- IR receiver +- Audio In/Out +- Video In/Out +- Serial Debug Port +- microUSB 5V 2A DC power-supply + +Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> +Signed-off-by: Chen-Yu Tsai <wens@csie.org> +--- + arch/arm64/boot/dts/allwinner/Makefile | 1 + + .../boot/dts/allwinner/sun50i-a64-nanopi-a64.dts | 207 +++++++++++++++++++++ + 2 files changed, 208 insertions(+) + create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts + +diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile +index 108f12c..c997b5c 100644 +--- a/arch/arm64/boot/dts/allwinner/Makefile ++++ b/arch/arm64/boot/dts/allwinner/Makefile +@@ -1,4 +1,5 @@ + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-bananapi-m64.dtb ++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-nanopi-a64.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-orangepi-win.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-sopine-baseboard.dtb +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts +new file mode 100644 +index 0000000..2beef9e +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts +@@ -0,0 +1,207 @@ ++/* ++ * Copyright (C) 2017 Jagan Teki <jteki@openedev.com> ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This library is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This library is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/dts-v1/; ++ ++#include "sun50i-a64.dtsi" ++ ++#include <dt-bindings/gpio/gpio.h> ++ ++/ { ++ model = "FriendlyARM NanoPi A64"; ++ compatible = "friendlyarm,nanopi-a64", "allwinner,sun50i-a64"; ++ ++ aliases { ++ serial0 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++}; ++ ++&ehci0 { ++ status = "okay"; ++}; ++ ++&ehci1 { ++ status = "okay"; ++}; ++ ++/* i2c1 connected with gpio headers like pine64, bananapi */ ++&i2c1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; ++ status = "disabled"; ++}; ++ ++&i2c1_pins { ++ bias-pull-up; ++}; ++ ++&mmc0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc0_pins>; ++ vmmc-supply = <®_dcdc1>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; ++ cd-inverted; ++ disable-wp; ++ bus-width = <4>; ++ status = "okay"; ++}; ++ ++&ohci0 { ++ status = "okay"; ++}; ++ ++&ohci1 { ++ status = "okay"; ++}; ++ ++&r_rsb { ++ status = "okay"; ++ ++ axp803: pmic@3a3 { ++ compatible = "x-powers,axp803"; ++ reg = <0x3a3>; ++ interrupt-parent = <&r_intc>; ++ interrupts = <0 IRQ_TYPE_LEVEL_LOW>; ++ }; ++}; ++ ++#include "axp803.dtsi" ++ ++®_aldo2 { ++ regulator-always-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-pl"; ++}; ++ ++®_aldo3 { ++ regulator-always-on; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-name = "vcc-pll-avcc"; ++}; ++ ++®_dcdc1 { ++ regulator-always-on; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-name = "vcc-3v"; ++}; ++ ++®_dcdc2 { ++ regulator-always-on; ++ regulator-min-microvolt = <1040000>; ++ regulator-max-microvolt = <1300000>; ++ regulator-name = "vdd-cpux"; ++}; ++ ++/* DCDC3 is polyphased with DCDC2 */ ++ ++®_dcdc5 { ++ regulator-always-on; ++ regulator-min-microvolt = <1500000>; ++ regulator-max-microvolt = <1500000>; ++ regulator-name = "vcc-dram"; ++}; ++ ++®_dcdc6 { ++ regulator-always-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1100000>; ++ regulator-name = "vdd-sys"; ++}; ++ ++®_dldo1 { ++ regulator-always-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-hdmi-dsi"; ++}; ++ ++®_dldo4 { ++ regulator-always-on; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-name = "vcc-pg-wifi-io"; ++}; ++ ++®_eldo1 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "cpvdd"; ++}; ++ ++®_fldo1 { ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-name = "vcc-1v2-hsic"; ++}; ++ ++/* ++ * The A64 chip cannot work without this regulator off, although ++ * it seems to be only driving the AR100 core. ++ * Maybe we don't still know well about CPUs domain. ++ */ ++®_fldo2 { ++ regulator-always-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1100000>; ++ regulator-name = "vdd-cpus"; ++}; ++ ++®_rtc_ldo { ++ regulator-name = "vcc-rtc"; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins_a>; ++ status = "okay"; ++}; ++ ++&usbphy { ++ status = "okay"; ++}; +-- +cgit v1.1 +From 4969efb28b4301b09aba621f30cf81c582c018a8 Mon Sep 17 00:00:00 2001 +From: Jagan Teki <jagan@amarulasolutions.com> +Date: Mon, 14 Aug 2017 16:16:04 +0530 +Subject: arm64: allwinner: a64: Add A64-OLinuXino initial support + +OLimex A64-OLinuXino is an open-source hardware board +using the Allwinner A64 SOC. + +OLimex A64-OLinuXino has +- A64 Quad-core Cortex-A53 64bit +- 1GB or 2GB RAM DDR3L @ 672Mhz +- microSD slot and 4/8/16GB eMMC +- Debug TTL UART +- HDMI +- LCD +- IR receiver +- 5V DC power supply + +Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> +Signed-off-by: Chen-Yu Tsai <wens@csie.org> +--- + arch/arm64/boot/dts/allwinner/Makefile | 1 + + .../boot/dts/allwinner/sun50i-a64-olinuxino.dts | 199 +++++++++++++++++++++ + 2 files changed, 200 insertions(+) + create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts + +diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile +index c997b5c..19c3fbd 100644 +--- a/arch/arm64/boot/dts/allwinner/Makefile ++++ b/arch/arm64/boot/dts/allwinner/Makefile +@@ -1,5 +1,6 @@ + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-bananapi-m64.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-nanopi-a64.dtb ++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-olinuxino.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-orangepi-win.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-sopine-baseboard.dtb +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts +new file mode 100644 +index 0000000..338e7861 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts +@@ -0,0 +1,199 @@ ++/* ++ * Copyright (C) 2017 Jagan Teki <jteki@openedev.com> ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This library is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This library is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/dts-v1/; ++ ++#include "sun50i-a64.dtsi" ++ ++#include <dt-bindings/gpio/gpio.h> ++ ++/ { ++ model = "Olimex A64-Olinuxino"; ++ compatible = "olimex,a64-olinuxino", "allwinner,sun50i-a64"; ++ ++ aliases { ++ serial0 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++}; ++ ++&mmc0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc0_pins>; ++ vmmc-supply = <®_dcdc1>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; ++ cd-inverted; ++ disable-wp; ++ bus-width = <4>; ++ status = "okay"; ++}; ++ ++&r_rsb { ++ status = "okay"; ++ ++ axp803: pmic@3a3 { ++ compatible = "x-powers,axp803"; ++ reg = <0x3a3>; ++ interrupt-parent = <&r_intc>; ++ interrupts = <0 IRQ_TYPE_LEVEL_LOW>; ++ }; ++}; ++ ++#include "axp803.dtsi" ++ ++®_aldo1 { ++ regulator-always-on; ++ regulator-min-microvolt = <2800000>; ++ regulator-max-microvolt = <2800000>; ++ regulator-name = "vcc-pe"; ++}; ++ ++®_aldo2 { ++ regulator-always-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-pl"; ++}; ++ ++®_aldo3 { ++ regulator-always-on; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-name = "vcc-pll-avcc"; ++}; ++ ++®_dcdc1 { ++ regulator-always-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-3v3"; ++}; ++ ++®_dcdc2 { ++ regulator-always-on; ++ regulator-min-microvolt = <1040000>; ++ regulator-max-microvolt = <1300000>; ++ regulator-name = "vdd-cpux"; ++}; ++ ++/* DCDC3 is polyphased with DCDC2 */ ++ ++®_dcdc5 { ++ regulator-always-on; ++ regulator-min-microvolt = <1500000>; ++ regulator-max-microvolt = <1500000>; ++ regulator-name = "vcc-ddr3"; ++}; ++ ++®_dcdc6 { ++ regulator-always-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1100000>; ++ regulator-name = "vdd-sys"; ++}; ++ ++®_dldo1 { ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-hdmi"; ++}; ++ ++®_dldo2 { ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-mipi"; ++}; ++ ++®_dldo3 { ++ regulator-min-microvolt = <2800000>; ++ regulator-max-microvolt = <2800000>; ++ regulator-name = "vcc-avdd-csi"; ++}; ++ ++®_dldo4 { ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-wifi-io"; ++}; ++ ++®_eldo1 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "cpvdd"; ++}; ++ ++®_eldo2 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc-dvdd-csi"; ++}; ++ ++®_fldo1 { ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-name = "vcc-1v2-hsic"; ++}; ++ ++/* ++ * The A64 chip cannot work without this regulator off, although ++ * it seems to be only driving the AR100 core. ++ * Maybe we don't still know well about CPUs domain. ++ */ ++®_fldo2 { ++ regulator-always-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1100000>; ++ regulator-name = "vdd-cpus"; ++}; ++ ++®_rtc_ldo { ++ regulator-name = "vcc-rtc"; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins_a>; ++ status = "okay"; ++}; +-- +cgit v1.1 diff --git a/baseconfig/arm/armv7/CONFIG_SUNXI_SRAM b/baseconfig/arm/CONFIG_SUNXI_SRAM index 526bd5868..526bd5868 100644 --- a/baseconfig/arm/armv7/CONFIG_SUNXI_SRAM +++ b/baseconfig/arm/CONFIG_SUNXI_SRAM diff --git a/kernel-aarch64-debug.config b/kernel-aarch64-debug.config index ce979b0fb..c5f3d5c80 100644 --- a/kernel-aarch64-debug.config +++ b/kernel-aarch64-debug.config @@ -5456,6 +5456,7 @@ CONFIG_SUNRPC=m CONFIG_SUNRPC_XPRT_RDMA=m CONFIG_SUNXI_CCU=y CONFIG_SUNXI_RSB=m +CONFIG_SUNXI_SRAM=y CONFIG_SUNXI_WATCHDOG=m # CONFIG_SURFACE_3_BUTTON is not set CONFIG_SUSPEND=y diff --git a/kernel-aarch64.config b/kernel-aarch64.config index 70a552b53..1b22c1fa3 100644 --- a/kernel-aarch64.config +++ b/kernel-aarch64.config @@ -5433,6 +5433,7 @@ CONFIG_SUNRPC=m CONFIG_SUNRPC_XPRT_RDMA=m CONFIG_SUNXI_CCU=y CONFIG_SUNXI_RSB=m +CONFIG_SUNXI_SRAM=y CONFIG_SUNXI_WATCHDOG=m # CONFIG_SURFACE_3_BUTTON is not set CONFIG_SUSPEND=y diff --git a/kernel.spec b/kernel.spec index 286926cc3..ee5578d8f 100644 --- a/kernel.spec +++ b/kernel.spec @@ -670,8 +670,9 @@ Patch334: arm64-socionext-96b-enablement.patch # ThunderX fixes Patch335: arm64-cavium-fixes.patch -# https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=c0d8832e78cbfd4a64b7112e34920af4b0b0e60e -# https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=ae2e972dae3cea795e9f8f94eb1601213c2d49f0 +Patch336: arm-exynos-fix-usb3.patch + +Patch337: arm64-aw64-devices.patch # 400 - IBM (ppc/s390x) patches @@ -725,6 +726,9 @@ Patch631: drm-i915-boost-GPU-clocks-if-we-miss-the-pageflip.patch # fix gnome 3.26+ not working under VirtualBox, submitted upstream, Cc: Stable Patch632: 0001-staging-vboxvideo-Fix-reporting-invalid-suggested-of.patch +# CVE-2017-15265 rhbz 1501878 1501880 +Patch633: 0001-ALSA-seq-Fix-use-after-free-at-creating-a-port.patch + # END OF PATCH DEFINITIONS %endif @@ -2282,6 +2286,15 @@ fi # # %changelog +* Mon Oct 16 2017 Justin M. Forbes <jforbes@fedoraproject.org> - 4.13.7-300 +- Linux v4.13.7 +- Fixes CVE-2017-5123 (rhbz 1500094 1501762) +- Fix CVE-2017-15265 (rhbz 1501878 1501880) + +* Sun Oct 15 2017 Peter Robinson <pbrobinson@fedoraproject.org> +- Fix USB-3 Superspeed negotiation on exynos5 hardware (rhbz 1487006) +- Some AllWinner A64 fixes and improvements + * Thu Oct 12 2017 Hans de Goede <jwrdegoede@fedoraproject.org> - Fix vboxvideo causing gnome 3.26+ to not work under VirtualBox @@ -1,3 +1,3 @@ SHA512 (linux-4.13.tar.xz) = a557c2f0303ae618910b7106ff63d9978afddf470f03cb72aa748213e099a0ecd5f3119aea6cbd7b61df30ca6ef3ec57044d524b7babbaabddf8b08b8bafa7d2 SHA512 (perf-man-4.13.tar.gz) = 9bcc2cd8e56ec583ed2d8e0b0c88e7a94035a1915e40b3177bb02d6c0f10ddd4df9b097b1f5af59efc624226b613e240ddba8ddc2156f3682f992d5455fc5c03 -SHA512 (patch-4.13.6.xz) = 40e111f3969b622f982bfb75f8c35aa59d9989a627a4511d8e0090b0c7bbcafcc90567434f5166ef2d17831f0beddb52762107e523414523e1877f67f66ca3f7 +SHA512 (patch-4.13.7.xz) = 4d96c655ca4c720b872e1a88ba9989a419880cb5fec2a4a9190077588066f205c5dce2591a76f26375f6f50001334ceb7631d489d3b24ca443d10e1e6879ed54 |