Merge remote-tracking branch 'origin/master' into rawhide-user-thl-vanilla-fedorakernel-4.14.0-0.rc2.git1.1.vanilla.knurd.1.fc27kernel-4.14.0-0.rc2.git1.1.vanilla.knurd.1.fc26

4 files changed, 61 insertions, 3 deletions

diff --git a/gitrev b/gitrev
index 78e4771b3..1fb6ea905 100644
--- a/gitrev
+++ b/gitrev
@@ -1 +1 @@
-0a8abd97dcda50e5d2c893a51733416534e95706
+e365806ac289457263a133bd32df8df49897f612
diff --git a/kernel.spec b/kernel.spec
index 138aaacd8..6f648abeb 100644
--- a/kernel.spec
+++ b/kernel.spec
@@ -77,7 +77,7 @@ Summary: The Linux kernel
 # The rc snapshot level
 %global rcrev 2
 # The git snapshot level
-%define gitrev 0
+%define gitrev 1
 # Set rpm version accordingly
 %define rpmversion 4.%{upstream_sublevel}.0
 %endif
@@ -133,7 +133,7 @@ Summary: The Linux kernel
 # Set debugbuildsenabled to 1 for production (build separate debug kernels)
 #  and 0 for rawhide (all kernels are debug kernels).
 # See also 'make debug' and 'make release'.
-%define debugbuildsenabled 1
+%define debugbuildsenabled 0
 
 # Want to build a vanilla kernel build without any non-upstream patches?
 %define with_vanilla %{?_without_vanilla: 0} %{?!_without_vanilla: 1}
@@ -613,6 +613,9 @@ Patch305: arm-imx6-hummingboard2.patch
 
 Patch306: arm64-Add-option-of-13-for-FORCE_MAX_ZONEORDER.patch
 
+# https://patchwork.kernel.org/patch/9967397/
+Patch307: tegra-Use-different-MSI-target-address-for-Tegra20.patch
+
 # https://patchwork.kernel.org/patch/9815555/
 # https://patchwork.kernel.org/patch/9815651/
 # https://patchwork.kernel.org/patch/9819885/
@@ -2213,6 +2216,13 @@ fi
 #
 #
 %changelog
+* Tue Sep 26 2017 Justin M. Forbes <jforbes@fedoraproject.org> - 4.14.0-0.rc2.git1.1
+- Linux v4.14-rc2-44-ge365806ac289
+- Reenable debugging options.
+
+* Mon Sep 25 2017 Peter Robinson <pbrobinson@fedoraproject.org>
+- Add patch to fix PCI on tegra20
+
 * Mon Sep 25 2017 Justin M. Forbes <jforbes@fedoraproject.org> - 4.14.0-0.rc2.git0.1
 - Linux v4.14-rc2
 
diff --git a/sources b/sources
index 8c3cf0667..26ebd9a64 100644
--- a/sources
+++ b/sources
@@ -1,3 +1,4 @@
 SHA512 (linux-4.13.tar.xz) = a557c2f0303ae618910b7106ff63d9978afddf470f03cb72aa748213e099a0ecd5f3119aea6cbd7b61df30ca6ef3ec57044d524b7babbaabddf8b08b8bafa7d2
 SHA512 (perf-man-4.13.tar.gz) = 9bcc2cd8e56ec583ed2d8e0b0c88e7a94035a1915e40b3177bb02d6c0f10ddd4df9b097b1f5af59efc624226b613e240ddba8ddc2156f3682f992d5455fc5c03
 SHA512 (patch-4.14-rc2.xz) = bfdf4ed88f7eeef35f723d886ea059a2fac69b7ea18313abe768d06674f6c36ca0579dd61170b9c91aeb7cc055af3c8330b15e092e8f4880ef6c8d93bd6cfa48
+SHA512 (patch-4.14-rc2-git1.xz) = 218386592cc5e0bf8622a0b01da57ca5518bba5a380977e79eb911bccfbdc4efbb0db2c47b9bba3e93839be478b8e0f2adba27d54dd0d9d9103b934631902ea6
diff --git a/tegra-Use-different-MSI-target-address-for-Tegra20.patch b/tegra-Use-different-MSI-target-address-for-Tegra20.patch
new file mode 100644
index 000000000..338693bcf
--- /dev/null
+++ b/tegra-Use-different-MSI-target-address-for-Tegra20.patch
@@ -0,0 +1,47 @@
+From patchwork Sat Sep 23 06:17:40 2017
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 7bit
+Subject: PCI: tegra: Use different MSI target address for Tegra20
+From: Thierry Reding <thierry.reding@gmail.com>
+X-Patchwork-Id: 9967397
+Message-Id: <20170923061740.6012-1-treding@nvidia.com>
+To: Bjorn Helgaas <bhelgaas@google.com>
+Cc: Thierry Reding <thierry.reding@gmail.com>,
+ Jonathan Hunter <jonathanh@nvidia.com>,
+ linux-pci@vger.kernel.org, linux-tegra@vger.kernel.org
+Date: Fri, 22 Sep 2017 23:17:40 -0700
+
+The Tegra20 PCIe controller has a different address range for MSI, so
+select a different target address.
+
+Fixes: d7bd554f27c9 ("PCI: tegra: Do not allocate MSI target memory")
+Signed-off-by: Thierry Reding <treding@nvidia.com>
+---
+ drivers/pci/host/pci-tegra.c | 12 +++++++++++-
+ 1 file changed, 11 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
+index e8e1ddbaabc9..5b02ea59524b 100644
+--- a/drivers/pci/host/pci-tegra.c
++++ b/drivers/pci/host/pci-tegra.c
+@@ -1563,8 +1563,18 @@ static int tegra_pcie_enable_msi(struct tegra_pcie *pcie)
+ 	 * none of the Tegra SoCs that contain this PCI host bridge can
+ 	 * address more than 16 GiB of system memory, the last 4 KiB of
+ 	 * these 1012 GiB is a good candidate.
++	 *
++	 * Unfortunately, Tegra20 is slightly different in that the physical
++	 * address for this MSI region is limited to the lower 32 bits of the
++	 * address map, so the address that we pick is going to have to be
++	 * located somewhere within the region addressable by the CPU and
++	 * on-SoC controllers. To be on the safe side, we select an address
++	 * from a region that is marked unused (0xf0010000 - 0xfffeffff).
+ 	 */
+-	msi->phys = 0xfcfffff000;
++	if (soc->msi_base_shift > 0)
++		msi->phys = 0xfcfffff000;
++	else
++		msi->phys = 0x00f0010000;
+ 
+ 	afi_writel(pcie, msi->phys >> soc->msi_base_shift, AFI_MSI_FPCI_BAR_ST);
+ 	afi_writel(pcie, msi->phys, AFI_MSI_AXI_BAR_ST);