PR909: add perf.hw_cache.* aliases

* tapset/perf.stp: Add 'em.
* man/tapset::perf.3stap: Document 'em a little.
* stapprobes.3stap.in: Fix .sample (not .samples) probe point typo.

3 files changed, 79 insertions, 5 deletions

diff --git a/man/tapset::perf.3stap b/man/tapset::perf.3stap
index 5aff9799..180a503c 100644
--- a/man/tapset::perf.3stap
+++ b/man/tapset::perf.3stap
@@ -18,10 +18,15 @@ tapset::perf \- systemtap perf probe points
 
 .SH DESCRIPTION
 
-This family of probe points is used to probe "perf events"
-on suitably configured kernels (2.6.33+).  It contains a
-number of aliases for the ABI-specified event type/config
-tuples.
+This family of probe points is used to probe "perf events" on suitably
+configured kernels (2.6.33+).  It contains a number of aliases for the
+ABI-specified event type/config tuples.
+
+The default sampling interval of the translator (1000000) is not
+overridden, so some of these probe points may fire very infrequently.
+Use the lower level
+.B perf.type(AA).config(BB).sample(CC)
+probe point if this is a problem.
 
 .TP
 .B perf.hw.*
@@ -53,6 +58,27 @@ probe perf.sw.alignment_faults
 probe perf.sw.emulation_faults
 .ESAMPLE
 
+
+.TP
+.B perf.hw_cache.TYPE.ACCESS.RESULT
+Hardware cache events, where available.  A subset of the following
+cartesian product may be available:
+.SAMPLE
+probe perf.hw_cache.l1d.*.*
+probe perf.hw_cache.l1i.*.*
+probe perf.hw_cache.ll.*.*
+probe perf.hw_cache.dtlb.*.*
+probe perf.hw_cache.itlb.*.*
+probe perf.hw_cache.bpu.*.*
+
+probe perf.hw_cache.*.read.*
+probe perf.hw_cache.*.write.*
+probe perf.hw_cache.*.prefetch.*
+
+probe perf.hw_cache.*.*.access
+probe perf.hw_cache.*.*.miss
+.ESAMPLE
+
 .SH SEE ALSO
 .IR stap (1),
 .IR stapprobes (3stap)
diff --git a/stapprobes.3stap.in b/stapprobes.3stap.in
index 394aa218..cb8c6060 100644
--- a/stapprobes.3stap.in
+++ b/stapprobes.3stap.in
@@ -800,7 +800,7 @@ structure, and are sampled at an interval governed by the
 These fields are made available to systemtap scripts using
 the following syntax:
 .SAMPLE
-probe perf.type(NN).config(MM).samples(XX)
+probe perf.type(NN).config(MM).sample(XX)
 probe perf.type(NN).config(MM)
 .ESAMPLE
 The range of valid type/config is described by the 
diff --git a/tapset/perf.stp b/tapset/perf.stp
index cdc4ef9d..ca49371f 100644
--- a/tapset/perf.stp
+++ b/tapset/perf.stp
@@ -27,3 +27,51 @@ probe perf.sw.page_faults_maj     = perf.type(1).config(6) { }
 probe perf.sw.alignment_faults    = perf.type(1).config(7) { }
 probe perf.sw.emulation_faults    = perf.type(1).config(8) { }
 
+// PERF_TYPE_TRACEPOINT: PR10745
+// probe perf.tracepoint.FOO      = perf.type(2).config(NNN) { }
+
+// PERF_TYPE_HW_CACHE, encoded into config (cache_op_result_id<<16 | cache_op_id<<8 | cache_id)
+probe perf.hw_cache.l1d.read.access      = perf.type(3).config(0x000000) {}
+probe perf.hw_cache.l1d.read.miss        = perf.type(3).config(0x010000) {}
+probe perf.hw_cache.l1d.write.access     = perf.type(3).config(0x000100) {}
+probe perf.hw_cache.l1d.write.miss       = perf.type(3).config(0x010100) {}
+probe perf.hw_cache.l1d.prefetch.access  = perf.type(3).config(0x000200) {}
+probe perf.hw_cache.l1d.prefetch.miss    = perf.type(3).config(0x010200) {}
+
+// according to kernel tools/perf/util/parse-events.c, WRITE not available
+probe perf.hw_cache.l1i.read.access      = perf.type(3).config(0x000001) {}
+probe perf.hw_cache.l1i.read.miss        = perf.type(3).config(0x010001) {}
+//probe perf.hw_cache.l1i.write.access     = perf.type(3).config(0x000101) {}
+//probe perf.hw_cache.l1i.write.miss       = perf.type(3).config(0x010101) {}
+probe perf.hw_cache.l1i.prefetch.access  = perf.type(3).config(0x000201) {}
+probe perf.hw_cache.l1i.prefetch.miss    = perf.type(3).config(0x010201) {}
+
+probe perf.hw_cache.ll.read.access       = perf.type(3).config(0x000002) {}
+probe perf.hw_cache.ll.read.miss         = perf.type(3).config(0x010002) {}
+probe perf.hw_cache.ll.write.access      = perf.type(3).config(0x000102) {}
+probe perf.hw_cache.ll.write.miss        = perf.type(3).config(0x010102) {}
+probe perf.hw_cache.ll.prefetch.access   = perf.type(3).config(0x000202) {}
+probe perf.hw_cache.ll.prefetch.miss     = perf.type(3).config(0x010202) {}
+
+probe perf.hw_cache.dtlb.read.access     = perf.type(3).config(0x000003) {}
+probe perf.hw_cache.dtlb.read.miss       = perf.type(3).config(0x010003) {}
+probe perf.hw_cache.dtlb.write.access    = perf.type(3).config(0x000103) {}
+probe perf.hw_cache.dtlb.write.miss      = perf.type(3).config(0x010103) {}
+probe perf.hw_cache.dtlb.prefetch.access = perf.type(3).config(0x000203) {}
+probe perf.hw_cache.dtlb.prefetch.miss   = perf.type(3).config(0x010203) {}
+
+// according to kernel tools/perf/util/parse-events.c, WRITE, PREFETCH not available
+probe perf.hw_cache.itlb.read.access     = perf.type(3).config(0x000004) {}
+probe perf.hw_cache.itlb.read.miss       = perf.type(3).config(0x010004) {}
+//probe perf.hw_cache.itlb.write.access    = perf.type(3).config(0x000104) {}
+//probe perf.hw_cache.itlb.write.miss      = perf.type(3).config(0x010104) {}
+//probe perf.hw_cache.itlb.prefetch.access = perf.type(3).config(0x000204) {}
+//probe perf.hw_cache.itlb.prefetch.miss   = perf.type(3).config(0x010204) {}
+
+// according to kernel tools/perf/util/parse-events.c, WRITE, PREFETCH not available
+probe perf.hw_cache.bpu.read.access      = perf.type(3).config(0x000005) {}
+probe perf.hw_cache.bpu.read.miss        = perf.type(3).config(0x010005) {}
+//probe perf.hw_cache.bpu.write.access     = perf.type(3).config(0x000105) {}
+//probe perf.hw_cache.bpu.write.miss       = perf.type(3).config(0x010105) {}
+//probe perf.hw_cache.bpu.prefetch.access  = perf.type(3).config(0x000205) {}
+//probe perf.hw_cache.bpu.prefetch.miss    = perf.type(3).config(0x010205) {}