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author	Stefan Metzmacher <metze@samba.org>	2013-02-28 17:07:28 +0100
committer	Jeremy Allison <jra@samba.org>	2013-03-01 11:59:42 -0800
commit	f45abeae40495460e29347ebc3c73b9ffece847d (patch)
tree	7ace1cb67180959eb3d08c74152c7b23e7db2aa7 /source4/scripting/python/samba_external
parent	ef8130fdbf50384dca3669ab27de4863490d5cb1 (diff)
download	samba-f45abeae40495460e29347ebc3c73b9ffece847d.tar.gz samba-f45abeae40495460e29347ebc3c73b9ffece847d.tar.xz samba-f45abeae40495460e29347ebc3c73b9ffece847d.zip

tevent: maintain a list of disabled events in the poll backend

We need to avoid passing pollfd.events == 0, to poll(), as it will report POLLERR and POLLHUP events, but our caller does not expect the event handler to be called. Signed-off-by: Stefan Metzmacher <metze@samba.org> Reviewed-by: Jeremy Allison <jra@samba.org>

Diffstat (limited to 'source4/scripting/python/samba_external')

0 files changed, 0 insertions, 0 deletions

/* * (C) Copyright 2003-2005 * Wolfgang Denk, DENX Software Engineering, <wd@denx.de> * * (C) Copyright 2003 * DAVE Srl * * http://www.dave-tech.it * http://www.wawnet.biz * mailto:info@wawnet.biz * * Credits: Stefan Roese, Wolfgang Denk * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ /* * board/config.h - configuration options, board specific */ #ifndef __CONFIG_H #define __CONFIG_H #define CONFIG_PPCHAMELEON_MODULE_BA 0 /* Basic Model */ #define CONFIG_PPCHAMELEON_MODULE_ME 1 /* Medium Model */ #define CONFIG_PPCHAMELEON_MODULE_HI 2 /* High-End Model */ #ifndef CONFIG_PPCHAMELEON_MODULE_MODEL #define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA #endif /* Only one of the following two symbols must be defined (default is 25 MHz) * CONFIG_PPCHAMELEON_CLK_25 * CONFIG_PPCHAMELEON_CLK_33 */ #if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33)) #define CONFIG_PPCHAMELEON_CLK_25 #endif #if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33)) #error "* Two external frequencies (SysClk) are defined! *" #endif #undef CONFIG_PPCHAMELEON_SMI712 /* * Debug stuff */ #undef __DEBUG_START_FROM_SRAM__ #define __DISABLE_MACHINE_EXCEPTION__ #ifdef __DEBUG_START_FROM_SRAM__ #define CONFIG_SYS_DUMMY_FLASH_SIZE 1024*1024*4 #endif /* * High Level Configuration Options * (easy to change) */ #define CONFIG_405EP 1 /* This is a PPC405 CPU */ #define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_PPCHAMELEONEVB 1 /* ...on a PPChameleonEVB board */ #define CONFIG_SYS_TEXT_BASE 0xFFFB0000 /* Reserve 320 kB for Monitor */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ #ifdef CONFIG_PPCHAMELEON_CLK_25 # define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ #elif (defined (CONFIG_PPCHAMELEON_CLK_33)) # define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ #else # error "* External frequency (SysClk) not defined! *" #endif #define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #undef CONFIG_BOOTARGS /* Ethernet stuff */ #define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */ #define CONFIG_ETHADDR 00:50:c2:1e:af:fe #define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:50:c2:1e:af:fd #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ #undef CONFIG_EXT_PHY #define CONFIG_NET_MULTI 1 #define CONFIG_PPC4xx_EMAC #define CONFIG_MII 1 /* MII PHY management */ #ifndef CONFIG_EXT_PHY #define CONFIG_PHY_ADDR 1 /* EMAC0 PHY address */ #define CONFIG_PHY1_ADDR 2 /* EMAC1 PHY address */ #else #define CONFIG_PHY_ADDR 2 /* PHY address */ #endif #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* * BOOTP options */ #define CONFIG_BOOTP_BOOTFILESIZE #define CONFIG_BOOTP_BOOTPATH #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME /* * Command line configuration. */ #include <config_cmd_default.h> #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP #define CONFIG_CMD_ELF #define CONFIG_CMD_EEPROM #define CONFIG_CMD_I2C #define CONFIG_CMD_IRQ #define CONFIG_CMD_JFFS2 #define CONFIG_CMD_MII #define CONFIG_CMD_NAND #define CONFIG_CMD_NFS #define CONFIG_CMD_PCI #define CONFIG_CMD_SNTP #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_RTC_M41T11 1 /* uses a M41T00 RTC */ #define CONFIG_SYS_I2C_RTC_ADDR 0x68 #define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* * SDRAM configuration (please see cpu/ppc/sdram.[ch]) */ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ /* SDRAM timings used in datasheet */ #define CONFIG_SYS_SDRAM_CL 2 #define CONFIG_SYS_SDRAM_tRP 20 #define CONFIG_SYS_SDRAM_tRC 65 #define CONFIG_SYS_SDRAM_tRCD 20 #undef CONFIG_SYS_SDRAM_tRFC /* * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ #ifdef CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #endif #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #endif #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #define CONFIG_CONS_INDEX 1 /* Use UART0 */ #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_serial_clock() #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ #define CONFIG_SYS_BASE_BAUD 691200 /* The following table includes the supported baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE \ { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ 57600, 115200, 230400, 460800, 921600 } #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ /*----------------------------------------------------------------------- * NAND-FLASH stuff *----------------------------------------------------------------------- */ /* * nand device 1 on dave (PPChameleonEVB) needs more time, * so we just introduce additional wait in nand_wait(), * effectively for both devices. */ #define PPCHAMELON_NAND_TIMER_HACK #define CONFIG_SYS_NAND0_BASE 0xFF400000 #define CONFIG_SYS_NAND1_BASE 0xFF000000 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, CONFIG_SYS_NAND1_BASE } #define NAND_BIG_DELAY_US 25 #define CONFIG_SYS_MAX_NAND_DEVICE 2 /* Max number of NAND devices */ #define CONFIG_SYS_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */ #define CONFIG_SYS_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ #define CONFIG_SYS_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ #define CONFIG_SYS_NAND0_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ #define CONFIG_SYS_NAND1_CE (0x80000000 >> 14) /* our CE is GPIO14 */ #define CONFIG_SYS_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */ #define CONFIG_SYS_NAND1_CLE (0x80000000 >> 15) /* our CLE is GPIO15 */ #define CONFIG_SYS_NAND1_ALE (0x80000000 >> 16) /* our ALE is GPIO16 */ #define MACRO_NAND_DISABLE_CE(nandptr) do \ { \ switch((unsigned long)nandptr) \ { \ case CONFIG_SYS_NAND0_BASE: \ out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CE); \ break; \ case CONFIG_SYS_NAND1_BASE: \ out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CE); \ break; \ } \ } while(0) #define MACRO_NAND_ENABLE_CE(nandptr) do \ { \ switch((unsigned long)nandptr) \ { \ case CONFIG_SYS_NAND0_BASE: \ out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CE); \ break; \ case CONFIG_SYS_NAND1_BASE: \ out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CE); \ break; \ } \ } while(0) #define MACRO_NAND_CTL_CLRALE(nandptr) do \ { \ switch((unsigned long)nandptr) \ { \ case CONFIG_SYS_NAND0_BASE: \ out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_ALE); \ break; \ case CONFIG_SYS_NAND1_BASE: \ out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_ALE); \ break; \ } \ } while(0) #define MACRO_NAND_CTL_SETALE(nandptr) do \ { \ switch((unsigned long)nandptr) \ { \ case CONFIG_SYS_NAND0_BASE: \ out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_ALE); \ break; \ case CONFIG_SYS_NAND1_BASE: \ out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_ALE); \ break; \ } \ } while(0) #define MACRO_NAND_CTL_CLRCLE(nandptr) do \ { \ switch((unsigned long)nandptr) \ { \ case CONFIG_SYS_NAND0_BASE: \ out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CLE); \ break; \ case CONFIG_SYS_NAND1_BASE: \ out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CLE); \ break; \ } \ } while(0) #define MACRO_NAND_CTL_SETCLE(nandptr) do { \ switch((unsigned long)nandptr) { \ case CONFIG_SYS_NAND0_BASE: \ out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CLE); \ break; \ case CONFIG_SYS_NAND1_BASE: \ out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CLE); \ break; \ } \ } while(0) /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- */ #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ #define PCI_HOST_FORCE 1 /* configure as pci host */ #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ #define CONFIG_PCI /* include pci support */ #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ #undef CONFIG_PCI_PNP /* do pci plug-and-play */ /* resource configuration */ #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */ #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: --- */ #define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ #define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ #define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ #define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* Reserve 256 kB for Monitor */ /* #define CONFIG_SYS_FLASH_BASE 0xFFFC0000 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_MONITOR_LEN (256 * 1024) */ /* Reserve 320 kB for Monitor */ #define CONFIG_SYS_FLASH_BASE 0xFFFB0000 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_MONITOR_LEN (320 * 1024) #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /*----------------------------------------------------------------------- * FLASH organization */ #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ /* * The following defines are added for buggy IOP480 byte interface. * All other boards should use the standard values (CPCI405 etc.) */ #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ /*----------------------------------------------------------------------- * Environment Variable setup */ #ifdef ENVIRONMENT_IN_EEPROM #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ #define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ #define CONFIG_ENV_SIZE 0x700 /* 2048-256 bytes may be used for env vars (total size of a CAT24WC16 is 2048 bytes)*/ #else /* DEFAULT: environment in flash, using redundand flash sectors */ #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ #define CONFIG_ENV_ADDR 0xFFFF8000 /* environment starts at the first small sector */ #define CONFIG_ENV_SECT_SIZE 0x2000 /* 8196 bytes may be used for env vars*/ #define CONFIG_ENV_ADDR_REDUND 0xFFFFA000 #define CONFIG_ENV_SIZE_REDUND 0x2000 #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ #endif /* ENVIRONMENT_IN_EEPROM */ #define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ #define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */ /*----------------------------------------------------------------------- * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ #define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */


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