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generated by cgit (git 2.34.1) at 2026-01-08 22:16:57 +0000

/*
 * Atheros AR71xx / AR9xxx GMAC driver
 *
 * Copyright (C) 2016 Marek Vasut <marex@denx.de>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <dm.h>
#include <errno.h>
#include <miiphy.h>
#include <malloc.h>
#include <linux/compiler.h>
#include <linux/err.h>
#include <linux/mii.h>
#include <wait_bit.h>
#include <asm/io.h>

#include <mach/ath79.h>

DECLARE_GLOBAL_DATA_PTR;

enum ag7xxx_model {
	AG7XXX_MODEL_AG933X,
	AG7XXX_MODEL_AG934X,
};

#define AG7XXX_ETH_CFG1				0x00
#define AG7XXX_ETH_CFG1_SOFT_RST		BIT(31)
#define AG7XXX_ETH_CFG1_RX_RST			BIT(19)
#define AG7XXX_ETH_CFG1_TX_RST			BIT(18)
#define AG7XXX_ETH_CFG1_LOOPBACK		BIT(8)
#define AG7XXX_ETH_CFG1_RX_EN			BIT(2)
#define AG7XXX_ETH_CFG1_TX_EN			BIT(0)

#define AG7XXX_ETH_CFG2				0x04
#define AG7XXX_ETH_CFG2_IF_1000			BIT(9)
#define AG7XXX_ETH_CFG2_IF_10_100		BIT(8)
#define AG7XXX_ETH_CFG2_IF_SPEED_MASK		(3 << 8)
#define AG7XXX_ETH_CFG2_HUGE_FRAME_EN		BIT(5)
#define AG7XXX_ETH_CFG2_LEN_CHECK		BIT(4)
#define AG7XXX_ETH_CFG2_PAD_CRC_EN		BIT(2)
#define AG7XXX_ETH_CFG2_FDX			BIT(0)

#define AG7XXX_ETH_MII_MGMT_CFG			0x20
#define AG7XXX_ETH_MII_MGMT_CFG_RESET		BIT(31)

#define AG7XXX_ETH_MII_MGMT_CMD			0x24
#define AG7XXX_ETH_MII_MGMT_CMD_READ		0x1

#define AG7XXX_ETH_MII_MGMT_ADDRESS		0x28
#define AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT	8

#define AG7XXX_ETH_MII_MGMT_CTRL		0x2c

#define AG7XXX_ETH_MII_MGMT_STATUS		0x30

#define AG7XXX_ETH_MII_MGMT_IND			0x34
#define AG7XXX_ETH_MII_MGMT_IND_INVALID		BIT(2)
#define AG7XXX_ETH_MII_MGMT_IND_BUSY		BIT(0)

#define AG7XXX_ETH_ADDR1			0x40
#define AG7XXX_ETH_ADDR2			0x44

#define AG7XXX_ETH_FIFO_CFG_0			0x48
#define AG7XXX_ETH_FIFO_CFG_1			0x4c
#define AG7XXX_ETH_FIFO_CFG_2			0x50
#define AG7XXX_ETH_FIFO_CFG_3			0x54
#define AG7XXX_ETH_FIFO_CFG_4			0x58
#define AG7XXX_ETH_FIFO_CFG_5			0x5c

#define AG7XXX_ETH_DMA_TX_CTRL			0x180
#define AG7XXX_ETH_DMA_TX_CTRL_TXE		BIT(0)

#define AG7XXX_ETH_DMA_TX_DESC			0x184

#define AG7XXX_ETH_DMA_TX_STATUS		0x188

#define AG7XXX_ETH_DMA_RX_CTRL			0x18c
#define AG7XXX_ETH_DMA_RX_CTRL_RXE		BIT(0)

#define AG7XXX_ETH_DMA_RX_DESC			0x190

#define AG7XXX_ETH_DMA_RX_STATUS		0x194

/* Custom register at 0x18070000 */
#define AG7XXX_GMAC_ETH_CFG			0x00
#define AG7XXX_ETH_CFG_SW_PHY_ADDR_SWAP		BIT(8)
#define AG7XXX_ETH_CFG_SW_PHY_SWAP		BIT(7)
#define AG7XXX_ETH_CFG_SW_ONLY_MODE		BIT(6)
#define AG7XXX_ETH_CFG_GE0_ERR_EN		BIT(5)
#define AG7XXX_ETH_CFG_MII_GE0_SLAVE		BIT(4)
#define AG7XXX_ETH_CFG_MII_GE0_MASTER		BIT(3)
#define AG7XXX_ETH_CFG_GMII_GE0			BIT(2)
#define AG7XXX_ETH_CFG_MII_GE0			BIT(1)
#define AG7XXX_ETH_CFG_RGMII_GE0		BIT(0)

#define CONFIG_TX_DESCR_NUM	8
#define CONFIG_RX_DESCR_NUM	8
#define CONFIG_ETH_BUFSIZE	2048
#define TX_TOTAL_BUFSIZE	(CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
#define RX_TOTAL_BUFSIZE	(CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)

/* DMA descriptor. */
struct ag7xxx_dma_desc {
	u32	data_addr;
#define AG7XXX_DMADESC_IS_EMPTY			BIT(31)
#define AG7XXX_DMADESC_FTPP_OVERRIDE_OFFSET	16
#define AG7XXX_DMADESC_PKT_SIZE_OFFSET		0
#define AG7XXX_DMADESC_PKT_SIZE_MASK		0xfff
	u32	config;
	u32	next_desc;
	u32	_pad[5];
};

struct ar7xxx_eth_priv {
	struct ag7xxx_dma_desc	tx_mac_descrtable[CONFIG_TX_DESCR_NUM];
	struct ag7xxx_dma_desc	rx_mac_descrtable[CONFIG_RX_DESCR_NUM];
	char		txbuffs[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
	char		rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);

	void __iomem		*regs;
	void __iomem		*phyregs;

	struct eth_device	*dev;
	struct phy_device	*phydev;
	struct mii_dev		*bus;

	u32			interface;
	u32			tx_currdescnum;
	u32			rx_currdescnum;
	enum ag7xxx_model	model;
};

/*
 * Switch and MDIO access
 */
static int ag7xxx_switch_read(struct mii_dev *bus, int addr, int reg, u16 *val)
{
	struct ar7xxx_eth_priv *priv = bus->priv;
	void __iomem *regs = priv->phyregs;
	int ret;

	writel(0x0, regs + AG7XXX_ETH_MII_MGMT_CMD);
	writel((addr << AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT) | reg,
	       regs + AG7XXX_ETH_MII_MGMT_ADDRESS);
	writel(AG7XXX_ETH_MII_MGMT_CMD_READ,
	       regs + AG7XXX_ETH_MII_MGMT_CMD);

	ret = wait_for_bit("ag7xxx", regs + AG7XXX_ETH_MII_MGMT_IND,
			   AG7XXX_ETH_MII_MGMT_IND_BUSY, 0, 1000, 0);
	if (ret)
		return ret;

	*val = readl(regs + AG7XXX_ETH_MII_MGMT_STATUS) & 0xffff;
	writel(0x0, regs + AG7XXX_ETH_MII_MGMT_CMD);

	return 0;
}

static int ag7xxx_switch_write(struct mii_dev *bus, int addr, int reg, u16 val)
{
	struct ar7xxx_eth_priv *priv = bus->priv;
	void __iomem *regs = priv->phyregs;
	int ret;

	writel((addr << AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT) | reg,
	       regs + AG7XXX_ETH_MII_MGMT_ADDRESS);
	writel(val, regs + AG7XXX_ETH_MII_MGMT_CTRL);

	ret = wait_for_bit("ag7xxx", regs + AG7XXX_ETH_MII_MGMT_IND,
			   AG7XXX_ETH_MII_MGMT_IND_BUSY, 0, 1000, 0);

	return ret;
}

static int ag7xxx_switch_reg_read(struct mii_dev *bus, int reg, u32 *val)
{
	struct ar7xxx_eth_priv *priv = bus->priv;
	u32 phy_addr;
	u32 reg_addr;
	u32 phy_temp;
	u32 reg_temp;
	u16 rv = 0;
	int ret;

	if (priv->model == AG7XXX_MODEL_AG933X) {
		phy_addr = 0x1f;
		reg_addr = 0x10;
	} else if (priv->model == AG7XXX_MODEL_AG934X) {
		phy_addr = 0x18;
		reg_addr = 0x00;
	} else
		return -EINVAL;

	ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9);
	if (ret)
		return ret;

	phy_temp = ((reg >> 6) & 0x7) | 0x10;
	reg_temp = (reg >> 1) & 0x1e;
	*val = 0;

	ret = ag7xxx_switch_read(bus, phy_temp, reg_temp | 0, &rv);
	if (ret < 0)
		return ret;
	*val |= rv;

	ret = ag7xxx_switch_read(bus, phy_temp, reg_temp | 1, &rv);
	if (ret < 0)
		return ret;
	*val |= (rv << 16);

	return 0;
}

static int ag7xxx_switch_reg_write(struct mii_dev *bus, int reg, u32 val)
{
	struct ar7xxx_eth_priv *priv = bus->priv;
	u32 phy_addr;
	u32 reg_addr;
	u32 phy_temp;
	u32 reg_temp;
	int ret;

	if (priv->model == AG7XXX_MODEL_AG933X) {
		phy_addr = 0x1f;
		reg_addr = 0x10;
	} else if (priv->model == AG7XXX_MODEL_AG934X) {
		phy_addr = 0x18;
		reg_addr = 0x00;
	} else
		return -EINVAL;

	ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9);
	if (ret)
		return ret;

	phy_temp = ((reg >> 6) & 0x7) | 0x10;
	reg_temp = (reg >> 1) & 0x1e;

	/*
	 * The switch on AR933x has some special register behavior, which
	 * expects particular write order of their nibbles:
	 *   0x40 ..... MSB first, LSB second
	 *   0x50 ..... MSB first, LSB second
	 *   0x98 ..... LSB first, MSB second
	 *   others ... don't care
	 */
	if ((priv->model == AG7XXX_MODEL_AG933X) && (reg == 0x98)) {
		ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 0, val & 0xffff);
		if (ret < 0)
			return ret;

		ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 1, val >> 16);
		if (ret < 0)
			return ret;
	} else {
		ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 1, val >> 16);
		if (ret < 0)
			return ret;

		ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 0, val & 0xffff);
		if (ret < 0)
			return ret;
	}

	return 0;
}

static u16 ag7xxx_mdio_rw(struct mii_dev *bus, int addr, int reg, u32 val)
{
	u32 data;

	/* Dummy read followed by PHY read/write command. */
	ag7xxx_switch_reg_read(bus, 0x98, &data);
	data = val | (reg << 16) | (addr << 21) | BIT(30) | BIT(31);
	ag7xxx_switch_reg_write(bus, 0x98, data);

	/* Wait for operation to finish */
	do {
		ag7xxx_switch_reg_read(bus, 0x98, &data);
	} while (data & BIT(31));

	return data & 0xffff;
}

static int ag7xxx_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
{
	return ag7xxx_mdio_rw(bus, addr, reg, BIT(27));
}

static int ag7xxx_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
			     u16 val)
{
	ag7xxx_mdio_rw(bus, addr, reg, val);
	return 0;
}

/*
 * DMA ring handlers
 */
static void ag7xxx_dma_clean_tx(struct udevice *dev)
{
	struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
	struct ag7xxx_dma_desc *curr, *next;
	u32 start, end;
	int i;

	for (i = 0; i < CONFIG_TX_DESCR_NUM; i++) {
		curr = &priv->tx_mac_descrtable[i];
		next = &priv->tx_mac_descrtable[(i + 1) % CONFIG_TX_DESCR_NUM];

		curr->data_addr = virt_to_phys(&priv->txbuffs[i * CONFIG_ETH_BUFSIZE]);
		curr->config = AG7XXX_DMADESC_IS_EMPTY;
		curr->next_desc = virt_to_phys(next);
	}

	priv->tx_currdescnum = 0;

	/* Cache: Flush descriptors, don't care about buffers. */
	start = (u32)(&priv->tx_mac_descrtable[0]);
	end = start + sizeof(priv->tx_mac_descrtable);
	flush_dcache_range(start, end);
}

static void ag7xxx_dma_clean_rx(struct udevice *dev)
{
	struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
	struct ag7xxx_dma_desc *curr, *next;
	u32 start, end;
	int i;

	for (i = 0; i < CONFIG_RX_DESCR_NUM; i++) {
		curr = &priv->rx_mac_descrtable[i];
		next = &priv->rx_mac_descrtable[(i + 1) % CONFIG_RX_DESCR_NUM];

		curr->data_addr = virt_to_phys(&priv->rxbuffs[i * CONFIG_ETH_BUFSIZE]);
		curr->config = AG7XXX_DMADESC_IS_EMPTY;
		curr->next_desc = virt_to_phys(next);
	}

	priv->rx_currdescnum = 0;