source4/scripting/python/wscript_build


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#!/usr/bin/env python

bld.SAMBA_LIBRARY('samba_python',
	source=[],
	deps='LIBPYTHON pytalloc-util pyrpc_util',
	grouping_library=True,
	private_library=True,
	pyext=True)

bld.SAMBA_SUBSYSTEM('LIBPYTHON',
	source='modules.c',
	public_deps='',
	init_function_sentinal='{NULL,NULL}',
	deps='talloc',
	pyext=True,
	)


bld.SAMBA_PYTHON('python_uuid',
	source='uuidmodule.c',
	deps='ndr',
	realname='uuid.so',
	enabled = float(bld.env.PYTHON_VERSION) <= 2.4
	)


bld.SAMBA_PYTHON('python_glue',
	source='pyglue.c',
	deps='pyparam_util samba-util netif pytalloc-util',
	realname='samba/_glue.so'
	)


# install out various python scripts for use by make test
bld.SAMBA_SCRIPT('samba_python',
                 pattern='samba/**/*.py',
                 installdir='python')

bld.INSTALL_WILDCARD('${PYTHONARCHDIR}', 'samba/**/*.py', flat=False)
/*
 * MPC85xx Internal Memory Map
 *
 * Copyright(c) 2002,2003 Motorola Inc.
 * Xianghua Xiao (x.xiao@motorola.com)
 *
 */

#ifndef __IMMAP_85xx__
#define __IMMAP_85xx__

#include <asm/types.h>
#include <asm/fsl_i2c.h>

/*
 * Local-Access Registers and ECM Registers(0x0000-0x2000)
 */
typedef struct ccsr_local_ecm {
	uint	ccsrbar;	/* 0x0 - Control Configuration Status Registers Base Address Register */
	char	res1[4];
	uint	altcbar;	/* 0x8 - Alternate Configuration Base Address Register */
	char	res2[4];
	uint	altcar;		/* 0x10 - Alternate Configuration Attribute Register */
	char	res3[12];
	uint	bptr;		/* 0x20 - Boot Page Translation Register */
	char	res4[3044];
	uint	lawbar0;	/* 0xc08 - Local Access Window 0 Base Address Register */
	char	res5[4];
	uint	lawar0;		/* 0xc10 - Local Access Window 0 Attributes Register */
	char	res6[20];
	uint	lawbar1;	/* 0xc28 - Local Access Window 1 Base Address Register */
	char	res7[4];
	uint	lawar1;		/* 0xc30 - Local Access Window 1 Attributes Register */
	char	res8[20];
	uint	lawbar2;	/* 0xc48 - Local Access Window 2 Base Address Register */
	char	res9[4];
	uint	lawar2;		/* 0xc50 - Local Access Window 2 Attributes Register */
	char	res10[20];
	uint	lawbar3;	/* 0xc68 - Local Access Window 3 Base Address Register */
	char	res11[4];
	uint	lawar3;		/* 0xc70 - Local Access Window 3 Attributes Register */
	char	res12[20];
	uint	lawbar4;	/* 0xc88 - Local Access Window 4 Base Address Register */
	char	res13[4];
	uint	lawar4;		/* 0xc90 - Local Access Window 4 Attributes Register */
	char	res14[20];
	uint	lawbar5;	/* 0xca8 - Local Access Window 5 Base Address Register */
	char	res15[4];
	uint	lawar5;		/* 0xcb0 - Local Access Window 5 Attributes Register */
	char	res16[20];
	uint	lawbar6;	/* 0xcc8 - Local Access Window 6 Base Address Register */
	char	res17[4];
	uint	lawar6;		/* 0xcd0 - Local Access Window 6 Attributes Register */
	char	res18[20];
	uint	lawbar7;	/* 0xce8 - Local Access Window 7 Base Address Register */
	char	res19[4];
	uint	lawar7;		/* 0xcf0 - Local Access Window 7 Attributes Register */
	char	res20[780];
	uint	eebacr;		/* 0x1000 - ECM CCB Address Configuration Register */
	char	res21[12];
	uint	eebpcr;		/* 0x1010 - ECM CCB Port Configuration Register */
	char	res22[3564];
	uint	eedr;		/* 0x1e00 - ECM Error Detect Register */
	char	res23[4];
	uint	eeer;		/* 0x1e08 - ECM Error Enable Register */
	uint	eeatr;		/* 0x1e0c - ECM Error Attributes Capture Register */
	uint	eeadr;		/* 0x1e10 - ECM Error Address Capture Register */
	char	res24[492];
} ccsr_local_ecm_t;

/*
 * DDR memory controller registers(0x2000-0x3000)
 */
typedef struct ccsr_ddr {
	uint	cs0_bnds;		/* 0x2000 - DDR Chip Select 0 Memory Bounds */
	char	res1[4];
	uint	cs1_bnds;		/* 0x2008 - DDR Chip Select 1 Memory Bounds */
	char	res2[4];
	uint	cs2_bnds;		/* 0x2010 - DDR Chip Select 2 Memory Bounds */
	char	res3[4];
	uint	cs3_bnds;		/* 0x2018 - DDR Chip Select 3 Memory Bounds */
	char	res4[100];
	uint	cs0_config;		/* 0x2080 - DDR Chip Select Configuration */
	uint	cs1_config;		/* 0x2084 - DDR Chip Select Configuration */
	uint	cs2_config;		/* 0x2088 - DDR Chip Select Configuration */
	uint	cs3_config;		/* 0x208c - DDR Chip Select Configuration */
	char	res5[112];
	uint	ext_refrec;		/* 0x2100 - DDR SDRAM Extended Refresh Recovery */
	uint	timing_cfg_0;		/* 0x2104 - DDR SDRAM Timing Configuration Register 0 */
	uint	timing_cfg_1;		/* 0x2108 - DDR SDRAM Timing Configuration Register 1 */
	uint	timing_cfg_2;		/* 0x210c - DDR SDRAM Timing Configuration Register 2 */
	uint	sdram_cfg;		/* 0x2110 - DDR SDRAM Control Configuration */
	uint	sdram_cfg_2;		/* 0x2114 - DDR SDRAM Control Configuration 2 */
	uint	sdram_mode;		/* 0x2118 - DDR SDRAM Mode Configuration */
	uint	sdram_mode_2;		/* 0x211c - DDR SDRAM Mode Configuration 2*/
	uint	sdram_md_cntl;		/* 0x2120 - DDR SDRAM Mode Control */
	uint	sdram_interval;		/* 0x2124 - DDR SDRAM Interval Configuration */
	uint	sdram_data_init;	/* 0x2128 - DDR SDRAM Data initialization */
	char	res6[4];
	uint	sdram_clk_cntl;		/* 0x2130 - DDR SDRAM Clock Control */
	char	res7[20];
	uint	init_address;		/* 0x2148 - DDR training initialization address */
	uint	init_ext_address;	/* 0x214C - DDR training initialization extended address */
	char	res8_1[2728];
	uint	ip_rev1;		/* 0x2BF8 - DDR IP Block Revision 1 */
	uint	ip_rev2;		/* 0x2BFC - DDR IP Block Revision 2 */
	char	res8_2[512];
	uint	data_err_inject_hi;	/* 0x2e00 - DDR Memory Data Path Error Injection Mask High */
	uint	data_err_inject_lo;	/* 0x2e04 - DDR Memory Data Path Error Injection Mask Low */
	uint	ecc_err_inject;		/* 0x2e08 - DDR Memory Data Path Error Injection Mask ECC */
	char	res9[20];
	uint	capture_data_hi;	/* 0x2e20 - DDR Memory Data Path Read Capture High */
	uint	capture_data_lo;	/* 0x2e24 - DDR Memory Data Path Read Capture Low */
	uint	capture_ecc;		/* 0x2e28 - DDR Memory Data Path Read Capture ECC */
	char	res10[20];
	uint	err_detect;		/* 0x2e40 - DDR Memory Error Detect */
	uint	err_disable;		/* 0x2e44 - DDR Memory Error Disable */
	uint	err_int_en;		/* 0x2e48 - DDR  */
	uint	capture_attributes;	/* 0x2e4c - DDR Memory Error Attributes Capture */
	uint	capture_address;	/* 0x2e50 - DDR Memory Error Address Capture */
	uint	capture_ext_address;	/* 0x2e54 - DDR Memory Error Extended Address Capture */
	uint	err_sbe;		/* 0x2e58 - DDR Memory Single-Bit ECC Error Management */
	char	res11[164];
	uint	debug_1;		/* 0x2f00 */
	uint	debug_2;
	uint	debug_3;
	uint	debug_4;
	char	res12[240];
} ccsr_ddr_t;

/*
 * I2C Registers(0x3000-0x4000)
 */
typedef struct ccsr_i2c {
	struct fsl_i2c	i2c[1];
	u8	res[4096 - 1 * sizeof(struct fsl_i2c)];
} ccsr_i2c_t;

#if defined(CONFIG_MPC8540) \
	|| defined(CONFIG_MPC8541) \
	|| defined(CONFIG_MPC8548) \
	|| defined(CONFIG_MPC8555)
/* DUART Registers(0x4000-0x5000) */
typedef struct ccsr_duart {
	char	res1[1280];
	u_char	urbr1_uthr1_udlb1;/* 0x4500 - URBR1, UTHR1, UDLB1 with the same address offset of 0x04500 */
	u_char	uier1_udmb1;	/* 0x4501 - UIER1, UDMB1 with the same address offset of 0x04501 */
	u_char	uiir1_ufcr1_uafr1;/* 0x4502 - UIIR1, UFCR1, UAFR1 with the same address offset of 0x04502 */
	u_char	ulcr1;		/* 0x4503 - UART1 Line Control Register */
	u_char	umcr1;		/* 0x4504 - UART1 Modem Control Register */
	u_char	ulsr1;		/* 0x4505 - UART1 Line Status Register */
	u_char	umsr1;		/* 0x4506 - UART1 Modem Status Register */
	u_char	uscr1;		/* 0x4507 - UART1 Scratch Register */
	char	res2[8];
	u_char	udsr1;		/* 0x4510 - UART1 DMA Status Register */
	char	res3[239];
	u_char	urbr2_uthr2_udlb2;/* 0x4600 - URBR2, UTHR2, UDLB2 with the same address offset of 0x04600 */
	u_char	uier2_udmb2;	/* 0x4601 - UIER2, UDMB2 with the same address offset of 0x04601 */
	u_char	uiir2_ufcr2_uafr2;/* 0x4602 - UIIR2, UFCR2, UAFR2 with the same address offset of 0x04602 */
	u_char	ulcr2;		/* 0x4603 - UART2 Line Control Register */
	u_char	umcr2;		/* 0x4604 - UART2 Modem Control Register */
	u_char	ulsr2;		/* 0x4605 - UART2 Line Status Register */
	u_char	umsr2;		/* 0x4606 - UART2 Modem Status Register */
	u_char	uscr2;		/* 0x4607 - UART2 Scratch Register */
	char	res4[8];
	u_char	udsr2;		/* 0x4610 - UART2 DMA Status Register */
	char	res5[2543];
} ccsr_duart_t;
#else /* MPC8560 uses UART on its CPM */
typedef struct ccsr_duart {
	char res[4096];
} ccsr_duart_t;
#endif

/* Local Bus Controller Registers(0x5000-0x6000) */
/* Omitting OCeaN(0x6000) and Reserved(0x7000) block */

typedef struct ccsr_lbc {
	uint	br0;		/* 0x5000 - LBC Base Register 0 */
	uint	or0;		/* 0x5004 - LBC Options Register 0 */
	uint	br1;		/* 0x5008 - LBC Base Register 1 */
	uint	or1;		/* 0x500c - LBC Options Register 1 */
	uint	br2;		/* 0x5010 - LBC Base Register 2 */
	uint	or2;		/* 0x5014 - LBC Options Register 2 */
	uint	br3;		/* 0x5018 - LBC Base Register 3 */
	uint	or3;		/* 0x501c - LBC Options Register 3 */
	uint	br4;		/* 0x5020 - LBC Base Register 4 */
	uint	or4;		/* 0x5024 - LBC Options Register 4 */
	uint	br5;		/* 0x5028 - LBC Base Register 5 */
	uint	or5;		/* 0x502c - LBC Options Register 5 */
	uint	br6;		/* 0x5030 - LBC Base Register 6 */
	uint	or6;		/* 0x5034 - LBC Options Register 6 */
	uint	br7;		/* 0x5038 - LBC Base Register 7 */
	uint	or7;		/* 0x503c - LBC Options Register 7 */
	char	res1[40];
	uint	mar;		/* 0x5068 - LBC UPM Address Register */
	char	res2[4];
	uint	mamr;		/* 0x5070 - LBC UPMA Mode Register */
	uint	mbmr;		/* 0x5074 - LBC UPMB Mode Register */
	uint	mcmr;		/* 0x5078 - LBC UPMC Mode Register */
	char	res3[8];
	uint	mrtpr;		/* 0x5084 - LBC Memory Refresh Timer Prescaler Register */
	uint	mdr;		/* 0x5088 - LBC UPM Data Register */
	char	res4[8];
	uint	lsdmr;		/* 0x5094 - LBC SDRAM Mode Register */
	char	res5[8];
	uint	lurt;		/* 0x50a0 - LBC UPM Refresh Timer */
	uint	lsrt;		/* 0x50a4 - LBC SDRAM Refresh Timer */
	char	res6[8];
	uint	ltesr;		/* 0x50b0 - LBC Transfer Error Status Register */
	uint	ltedr;		/* 0x50b4 - LBC Transfer Error Disable Register */
	uint	lteir;		/* 0x50b8 - LBC Transfer Error Interrupt Register */
	uint	lteatr;		/* 0x50bc - LBC Transfer Error Attributes Register */
	uint	ltear;		/* 0x50c0 - LBC Transfer Error Address Register */
	char	res7[12];
	uint	lbcr;		/* 0x50d0 - LBC Configuration Register */
	uint	lcrr;		/* 0x50d4 - LBC Clock Ratio Register */
	char	res8[12072];
} ccsr_lbc_t;

/*
 * PCI Registers(0x8000-0x9000)
 */
typedef struct ccsr_pcix {
	uint	cfg_addr;	/* 0x8000 - PCIX Configuration Address Register */
	uint	cfg_data;	/* 0x8004 - PCIX Configuration Data Register */
	uint	int_ack;	/* 0x8008 - PCIX Interrupt Acknowledge Register */
	char	res1[3060];
	uint	potar0;		/* 0x8c00 - PCIX Outbound Transaction Address Register 0 */
	uint	potear0;	/* 0x8c04 - PCIX Outbound Translation Extended Address Register 0 */
	uint	powbar0;	/* 0x8c08 - PCIX Outbound Window Base Address Register 0 */
	uint	powbear0;	/* 0x8c0c - PCIX Outbound Window Base Extended Address Register 0 */
	uint	powar0;		/* 0x8c10 - PCIX Outbound Window Attributes Register 0 */
	char	res2[12];
	uint	potar1;		/* 0x8c20 - PCIX Outbound Transaction Address Register 1 */
	uint	potear1;	/* 0x8c24 - PCIX Outbound Translation Extended Address Register 1 */
	uint	powbar1;	/* 0x8c28 - PCIX Outbound Window Base Address Register 1 */
	uint	powbear1;	/* 0x8c2c - PCIX Outbound Window Base Extended Address Register 1 */
	uint	powar1;		/* 0x8c30 - PCIX Outbound Window Attributes Register 1 */
	char	res3[12];
	uint	potar2;		/* 0x8c40 - PCIX Outbound Transaction Address Register 2 */
	uint	potear2;	/* 0x8c44 - PCIX Outbound Translation Extended Address Register 2 */
	uint	powbar2;	/* 0x8c48 - PCIX Outbound Window Base Address Register 2 */
	uint	powbear2;	/* 0x8c4c - PCIX Outbound Window Base Extended Address Register 2 */
	uint	powar2;		/* 0x8c50 - PCIX Outbound Window Attributes Register 2 */
	char	res4[12];
	uint	potar3;		/* 0x8c60 - PCIX Outbound Transaction Address Register 3 */
	uint	potear3;	/* 0x8c64 - PCIX Outbound Translation Extended Address Register 3 */
	uint	powbar3;	/* 0x8c68 - PCIX Outbound Window Base Address Register 3 */
	uint	powbear3;	/* 0x8c6c - PCIX Outbound Window Base Extended Address Register 3 */
	uint	powar3;		/* 0x8c70 - PCIX Outbound Window Attributes Register 3 */
	char	res5[12];
	uint	potar4;		/* 0x8c80 - PCIX Outbound Transaction Address Register 4 */
	uint	potear4;	/* 0x8c84 - PCIX Outbound Translation Extended Address Register 4 */
	uint	powbar4;	/* 0x8c88 - PCIX Outbound Window Base Address Register 4 */
	uint	powbear4;	/* 0x8c8c - PCIX Outbound Window Base Extended Address Register 4 */
	uint	powar4;		/* 0x8c90 - PCIX Outbound Window Attributes Register 4 */
	char	res6[268];
	uint	pitar3;		/* 0x8da0 - PCIX Inbound Translation Address Register 3  */
	uint	pitear3;	/* 0x8da4 - PCIX Inbound Translation Extended Address Register 3 */
	uint	piwbar3;	/* 0x8da8 - PCIX Inbound Window Base Address Register 3 */
	uint	piwbear3;	/* 0x8dac - PCIX Inbound Window Base Extended Address Register 3 */
	uint	piwar3;		/* 0x8db0 - PCIX Inbound Window Attributes Register 3 */
	char	res7[12];
	uint	pitar2;		/* 0x8dc0 - PCIX Inbound Translation Address Register 2  */
	uint	pitear2;	/* 0x8dc4 - PCIX Inbound Translation Extended Address Register 2 */
	uint	piwbar2;	/* 0x8dc8 - PCIX Inbound Window Base Address Register 2 */
	uint	piwbear2;	/* 0x8dcc - PCIX Inbound Window Base Extended Address Register 2 */
	uint	piwar2;		/* 0x8dd0 - PCIX Inbound Window Attributes Register 2 */
	char	res8[12];
	uint	pitar1;		/* 0x8de0 - PCIX Inbound Translation Address Register 1  */
	uint	pitear1;	/* 0x8de4 - PCIX Inbound Translation Extended Address Register 1 */
	uint	piwbar1;	/* 0x8de8 - PCIX Inbound Window Base Address Register 1 */
	char	res9[4];
	uint	piwar1;		/* 0x8df0 - PCIX Inbound Window Attributes Register 1 */
	char	res10[12];
	uint	pedr;		/* 0x8e00 - PCIX Error Detect Register */
	uint	pecdr;		/* 0x8e04 - PCIX Error Capture Disable Register */
	uint	peer;		/* 0x8e08 - PCIX Error Enable Register */
	uint	peattrcr;	/* 0x8e0c - PCIX Error Attributes Capture Register */
	uint	peaddrcr;	/* 0x8e10 - PCIX Error Address Capture Register */
	uint	peextaddrcr;	/* 0x8e14 - PCIX  Error Extended Address Capture Register */
	uint	pedlcr;		/* 0x8e18 - PCIX Error Data Low Capture Register */
	uint	pedhcr;		/* 0x8e1c - PCIX Error Error Data High Capture Register */
	uint	gas_timr;	/* 0x8e20 - PCIX Gasket Timer Register */
	char	res11[476];
} ccsr_pcix_t;

#define PCIX_COMMAND	0x62
#define POWAR_EN	0x80000000
#define POWAR_IO_READ	0x00080000
#define POWAR_MEM_READ	0x00040000
#define POWAR_IO_WRITE	0x00008000
#define POWAR_MEM_WRITE	0x00004000
#define POWAR_MEM_512M	0x0000001c
#define POWAR_IO_1M	0x00000013

#define PIWAR_EN	0x80000000
#define PIWAR_PF	0x20000000
#define PIWAR_LOCAL	0x00f00000
#define PIWAR_READ_SNOOP	0x00050000
#define PIWAR_WRITE_SNOOP	0x00005000
#define PIWAR_MEM_2G		0x0000001e


/*
 * L2 Cache Registers(0x2_0000-0x2_1000)
 */
typedef struct ccsr_l2cache {
	uint	l2ctl;		/* 0x20000 - L2 configuration register 0 */
	char	res1[12];
	uint	l2cewar0;	/* 0x20010 - L2 cache external write address register 0 */
	char	res2[4];
	uint	l2cewcr0;	/* 0x20018 - L2 cache external write control register 0 */
	char	res3[4];
	uint	l2cewar1;	/* 0x20020 - L2 cache external write address register 1 */
	char	res4[4];
	uint	l2cewcr1;	/* 0x20028 - L2 cache external write control register 1 */
	char	res5[4];
	uint	l2cewar2;	/* 0x20030 - L2 cache external write address register 2 */
	char	res6[4];
	uint	l2cewcr2;	/* 0x20038 - L2 cache external write control register 2 */
	char	res7[4];
	uint	l2cewar3;	/* 0x20040 - L2 cache external write address register 3 */
	char	res8[4];
	uint	l2cewcr3;	/* 0x20048 - L2 cache external write control register 3 */
	char	res9[180];
	uint	l2srbar0;	/* 0x20100 - L2 memory-mapped SRAM base address register 0 */
	char	res10[4];
	uint	l2srbar1;	/* 0x20108 - L2 memory-mapped SRAM base address register 1 */
	char	res11[3316];
	uint	l2errinjhi;	/* 0x20e00 - L2 error injection mask high register */
	uint	l2errinjlo;	/* 0x20e04 - L2 error injection mask low register */
	uint	l2errinjctl;	/* 0x20e08 - L2 error injection tag/ECC control register */
	char	res12[20];
	uint	l2captdatahi;	/* 0x20e20 - L2 error data high capture register */
	uint	l2captdatalo;	/* 0x20e24 - L2 error data low capture register */
	uint	l2captecc;	/* 0x20e28 - L2 error ECC capture register */
	char	res13[20];
	uint	l2errdet;	/* 0x20e40 - L2 error detect register */
	uint	l2errdis;	/* 0x20e44 - L2 error disable register */
	uint	l2errinten;	/* 0x20e48 - L2 error interrupt enable register */
	uint	l2errattr;	/* 0x20e4c - L2 error attributes capture register */
	uint	l2erraddr;	/* 0x20e50 - L2 error address capture register */
	char	res14[4];
	uint	l2errctl;	/* 0x20e58 - L2 error control register */
	char	res15[420];
} ccsr_l2cache_t;

/*
 * DMA Registers(0x2_1000-0x2_2000)
 */
typedef struct ccsr_dma {
	char	res1[256];
	uint	mr0;		/* 0x21100 - DMA 0 Mode Register */
	uint	sr0;		/* 0x21104 - DMA 0 Status Register */
	char	res2[4];
	uint	clndar0;	/* 0x2110c - DMA 0 Current Link Descriptor Address Register */
	uint	satr0;		/* 0x21110 - DMA 0 Source Attributes Register */
	uint	sar0;		/* 0x21114 - DMA 0 Source Address Register */
	uint	datr0;		/* 0x21118 - DMA 0 Destination Attributes Register */
	uint	dar0;		/* 0x2111c - DMA 0 Destination Address Register */
	uint	bcr0;		/* 0x21120 - DMA 0 Byte Count Register */
	char	res3[4];
	uint	nlndar0;	/* 0x21128 - DMA 0 Next Link Descriptor Address Register */
	char	res4[8];
	uint	clabdar0;	/* 0x21134 - DMA 0 Current List - Alternate Base Descriptor Address Register */
	char	res5[4];
	uint	nlsdar0;	/* 0x2113c - DMA 0 Next List Descriptor Address Register */
	uint	ssr0;		/* 0x21140 - DMA 0 Source Stride Register */
	uint	dsr0;		/* 0x21144 - DMA 0 Destination Stride Register */
	char	res6[56];
	uint	mr1;		/* 0x21180 - DMA 1 Mode Register */
	uint	sr1;		/* 0x21184 - DMA 1 Status Register */
	char	res7[4];
	uint	clndar1;	/* 0x2118c - DMA 1 Current Link Descriptor Address Register */
	uint	satr1;		/* 0x21190 - DMA 1 Source Attributes Register */
	uint	sar1;		/* 0x21194 - DMA 1 Source Address Register */
	uint	datr1;		/* 0x21198 - DMA 1 Destination Attributes Register */
	uint	dar1;		/* 0x2119c - DMA 1 Destination Address Register */
	uint	bcr1;		/* 0x211a0 - DMA 1 Byte Count Register */
	char	res8[4];
	uint	nlndar1;	/* 0x211a8 - DMA 1 Next Link Descriptor Address Register */
	char	res9[8];
	uint	clabdar1;	/* 0x211b4 - DMA 1 Current List - Alternate Base Descriptor Address Register */
	char	res10[4];
	uint	nlsdar1;	/* 0x211bc - DMA 1 Next List Descriptor Address Register */
	uint	ssr1;		/* 0x211c0 - DMA 1 Source Stride Register */
	uint	dsr1;		/* 0x211c4 - DMA 1 Destination Stride Register */
	char	res11[56];
	uint	mr2;		/* 0x21200 - DMA 2 Mode Register */
	uint	sr2;		/* 0x21204 - DMA 2 Status Register */
	char	res12[4];
	uint	clndar2;	/* 0x2120c - DMA 2 Current Link Descriptor Address Register */
	uint	satr2;		/* 0x21210 - DMA 2 Source Attributes Register */
	uint	sar2;		/* 0x21214 - DMA 2 Source Address Register */
	uint	datr2;		/* 0x21218 - DMA 2 Destination Attributes Register */
	uint	dar2;		/* 0x2121c - DMA 2 Destination Address Register */
	uint	bcr2;		/* 0x21220 - DMA 2 Byte Count Register */
	char	res13[4];
	uint	nlndar2;	/* 0x21228 - DMA 2 Next Link Descriptor Address Register */
	char	res14[8];
	uint	clabdar2;	/* 0x21234 - DMA 2 Current List - Alternate Base Descriptor Address Register */
	char	res15[4];
	uint	nlsdar2;	/* 0x2123c - DMA 2 Next List Descriptor Address Register */
	uint	ssr2;		/* 0x21240 - DMA 2 Source Stride Register */
	uint	dsr2;		/* 0x21244 - DMA 2 Destination Stride Register */
	char	res16[56];
	uint	mr3;		/* 0x21280 - DMA 3 Mode Register */
	uint	sr3;		/* 0x21284 - DMA 3 Status Register */
	char	res17[4];
	uint	clndar3;	/* 0x2128c - DMA 3 Current Link Descriptor Address Register */
	uint	satr3;		/* 0x21290 - DMA 3 Source Attributes Register */
	uint	sar3;		/* 0x21294 - DMA 3 Source Address Register */
	uint	datr3;		/* 0x21298 - DMA 3 Destination Attributes Register */
	uint	dar3;		/* 0x2129c - DMA 3 Destination Address Register */
	uint	bcr3;		/* 0x212a0 - DMA 3 Byte Count Register */
	char	res18[4];
	uint	nlndar3;	/* 0x212a8 - DMA 3 Next Link Descriptor Address Register */
	char	res19[8];
	uint	clabdar3;	/* 0x212b4 - DMA 3 Current List - Alternate Base Descriptor Address Register */
	char	res20[4];
	uint	nlsdar3;	/* 0x212bc - DMA 3 Next List Descriptor Address Register */
	uint	ssr3;		/* 0x212c0 - DMA 3 Source Stride Register */
	uint	dsr3;		/* 0x212c4 - DMA 3 Destination Stride Register */
	char	res21[56];
	uint	dgsr;		/* 0x21300 - DMA General Status Register */
	char	res22[11516];
} ccsr_dma_t;

/*
 * tsec1 tsec2: 24000-26000
 */
typedef struct ccsr_tsec {
	char	res1[16];
	uint	ievent;		/* 0x24010 - Interrupt Event Register */
	uint	imask;		/* 0x24014 - Interrupt Mask Register */
	uint	edis;		/* 0x24018 - Error Disabled Register */
	char	res2[4];
	uint	ecntrl;		/* 0x24020 - Ethernet Control Register */
	uint	minflr;		/* 0x24024 - Minimum Frame Length Register */
	uint	ptv;		/* 0x24028 - Pause Time Value Register */
	uint	dmactrl;	/* 0x2402c - DMA Control Register */
	uint	tbipa;		/* 0x24030 - TBI PHY Address Register */
	char	res3[88];
	uint	fifo_tx_thr;		/* 0x2408c - FIFO transmit threshold register */
	char	res4[8];
	uint	fifo_tx_starve;		/* 0x24098 - FIFO transmit starve register */
	uint	fifo_tx_starve_shutoff;		/* 0x2409c - FIFO transmit starve shutoff register */
	char	res5[96];
	uint	tctrl;		/* 0x24100 - Transmit Control Register */
	uint	tstat;		/* 0x24104 - Transmit Status Register */
	char	res6[4];
	uint	tbdlen;		/* 0x2410c - Transmit Buffer Descriptor Data Length Register */
	char	res7[16];
	uint	ctbptrh;	/* 0x24120 - Current Transmit Buffer Descriptor Pointer High Register */
	uint	ctbptr;		/* 0x24124 - Current Transmit Buffer Descriptor Pointer Register */
	char	res8[88];
	uint	tbptrh;		/* 0x24180 - Transmit Buffer Descriptor Pointer High Register */
	uint	tbptr;		/* 0x24184 - Transmit Buffer Descriptor Pointer Low Register */
	char	res9[120];
	uint	tbaseh;		/* 0x24200 - Transmit Descriptor Base Address High Register */
	uint	tbase;		/* 0x24204 - Transmit Descriptor Base Address Register */
	char	res10[168];
	uint	ostbd;		/* 0x242b0 - Out-of-Sequence Transmit Buffer Descriptor Register */
	uint	ostbdp;		/* 0x242b4 - Out-of-Sequence Transmit Data Buffer Pointer Register */
	uint	os32tbdp;	/* 0x242b8 - Out-of-Sequence 32 Bytes Transmit Data Buffer Pointer Low Register */
	uint	os32iptrh;	/* 0x242bc - Out-of-Sequence 32 Bytes Transmit Insert Pointer High Register */
	uint	os32iptrl;	/* 0x242c0 - Out-of-Sequence 32 Bytes Transmit Insert Pointer Low Register */
	uint	os32tbdr;	/* 0x242c4 - Out-of-Sequence 32 Bytes Transmit Reserved Register */
	uint	os32iil;	/* 0x242c8 - Out-of-Sequence 32 Bytes Transmit Insert Index/Length Register */
	char	res11[52];
	uint	rctrl;		/* 0x24300 - Receive Control Register */
	uint	rstat;		/* 0x24304 - Receive Status Register */
	char	res12[4];
	uint	rbdlen;		/* 0x2430c - RxBD Data Length Register */
	char	res13[16];
	uint	crbptrh;	/* 0x24320 - Current Receive Buffer Descriptor Pointer High */
	uint	crbptr;		/* 0x24324 - Current Receive Buffer Descriptor Pointer */
	char	res14[24];
	uint	mrblr;		/* 0x24340 - Maximum Receive Buffer Length Register */
	uint	mrblr2r3;	/* 0x24344 - Maximum Receive Buffer Length R2R3 Register */
	char	res15[56];
	uint	rbptrh;		/* 0x24380 - Receive Buffer Descriptor Pointer High 0 */
	uint	rbptr;		/* 0x24384 - Receive Buffer Descriptor Pointer */
	uint	rbptrh1;	/* 0x24388 - Receive Buffer Descriptor Pointer High 1 */
	uint	rbptrl1;	/* 0x2438c - Receive Buffer Descriptor Pointer Low 1 */
	uint	rbptrh2;	/* 0x24390 - Receive Buffer Descriptor Pointer High 2 */
	uint	rbptrl2;	/* 0x24394 - Receive Buffer Descriptor Pointer Low 2 */
	uint	rbptrh3;	/* 0x24398 - Receive Buffer Descriptor Pointer High 3 */
	uint	rbptrl3;	/* 0x2439c - Receive Buffer Descriptor Pointer Low 3 */
	char	res16[96];
	uint	rbaseh;		/* 0x24400 - Receive Descriptor Base Address High 0 */
	uint	rbase;		/* 0x24404 - Receive Descriptor Base Address */
	uint	rbaseh1;	/* 0x24408 - Receive Descriptor Base Address High 1 */
	uint	rbasel1;	/* 0x2440c - Receive Descriptor Base Address Low 1 */
	uint	rbaseh2;	/* 0x24410 - Receive Descriptor Base Address High 2 */
	uint	rbasel2;	/* 0x24414 - Receive Descriptor Base Address Low 2 */
	uint	rbaseh3;	/* 0x24418 - Receive Descriptor Base Address High 3 */
	uint	rbasel3;	/* 0x2441c - Receive Descriptor Base Address Low 3 */
	char	res17[224];
	uint	maccfg1;	/* 0x24500 - MAC Configuration 1 Register */
	uint	maccfg2;	/* 0x24504 - MAC Configuration 2 Register */
	uint	ipgifg;		/* 0x24508 - Inter Packet Gap/Inter Frame Gap Register */
	uint	hafdup;		/* 0x2450c - Half Duplex Register */
	uint	maxfrm;		/* 0x24510 - Maximum Frame Length Register */
	char	res18[12];
	uint	miimcfg;	/* 0x24520 - MII Management Configuration Register */
	uint	miimcom;	/* 0x24524 - MII Management Command Register */
	uint	miimadd;	/* 0x24528 - MII Management Address Register */
	uint	miimcon;	/* 0x2452c - MII Management Control Register */
	uint	miimstat;	/* 0x24530 - MII Management Status Register */
	uint	miimind;	/* 0x24534 - MII Management Indicator Register */
	char	res19[4];
	uint	ifstat;		/* 0x2453c - Interface Status Register */
	uint	macstnaddr1;	/* 0x24540 - Station Address Part 1 Register */
	uint	macstnaddr2;	/* 0x24544 - Station Address Part 2 Register */
	char	res20[312];
	uint	tr64;		/* 0x24680 - Transmit and Receive 64-byte Frame Counter */
	uint	tr127;		/* 0x24684 - Transmit and Receive 65-127 byte Frame Counter */
	uint	tr255;		/* 0x24688 - Transmit and Receive 128-255 byte Frame Counter */
	uint	tr511;		/* 0x2468c - Transmit and Receive 256-511 byte Frame Counter */
	uint	tr1k;		/* 0x24690 - Transmit and Receive 512-1023 byte Frame Counter */
	uint	trmax;		/* 0x24694 - Transmit and Receive 1024-1518 byte Frame Counter */
	uint	trmgv;		/* 0x24698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */
	uint	rbyt;		/* 0x2469c - Receive Byte Counter */
	uint	rpkt;		/* 0x246a0 - Receive Packet Counter */
	uint	rfcs;		/* 0x246a4 - Receive FCS Error Counter */
	uint	rmca;		/* 0x246a8 - Receive Multicast Packet Counter */
	uint	rbca;		/* 0x246ac - Receive Broadcast Packet Counter */
	uint	rxcf;		/* 0x246b0 - Receive Control Frame Packet Counter */
	uint	rxpf;		/* 0x246b4 - Receive Pause Frame Packet Counter */
	uint	rxuo;		/* 0x246b8 - Receive Unknown OP Code Counter */
	uint	raln;		/* 0x246bc - Receive Alignment Error Counter */
	uint	rflr;		/* 0x246c0 - Receive Frame Length Error Counter */
	uint	rcde;		/* 0x246c4 - Receive Code Error Counter */
	uint	rcse;		/* 0x246c8 - Receive Carrier Sense Error Counter */
	uint	rund;		/* 0x246cc - Receive Undersize Packet Counter */
	uint	rovr;		/* 0x246d0 - Receive Oversize Packet Counter */
	uint	rfrg;		/* 0x246d4 - Receive Fragments Counter */
	uint	rjbr;		/* 0x246d8 - Receive Jabber Counter */
	uint	rdrp;		/* 0x246dc - Receive Drop Counter */
	uint	tbyt;		/* 0x246e0 - Transmit Byte Counter Counter */
	uint	tpkt;		/* 0x246e4 - Transmit Packet Counter */
	uint	tmca;		/* 0x246e8 - Transmit Multicast Packet Counter */
	uint	tbca;		/* 0x246ec - Transmit Broadcast Packet Counter */
	uint	txpf;		/* 0x246f0 - Transmit Pause Control Frame Counter */
	uint	tdfr;		/* 0x246f4 - Transmit Deferral Packet Counter */
	uint	tedf;		/* 0x246f8 - Transmit Excessive Deferral Packet Counter */
	uint	tscl;		/* 0x246fc - Transmit Single Collision Packet Counter */
	uint	tmcl;		/* 0x24700 - Transmit Multiple Collision Packet Counter */
	uint	tlcl;		/* 0x24704 - Transmit Late Collision Packet Counter */
	uint	txcl;		/* 0x24708 - Transmit Excessive Collision Packet Counter */
	uint	tncl;		/* 0x2470c - Transmit Total Collision Counter */
	char	res21[4];
	uint	tdrp;		/* 0x24714 - Transmit Drop Frame Counter */
	uint	tjbr;		/* 0x24718 - Transmit Jabber Frame Counter */
	uint	tfcs;		/* 0x2471c - Transmit FCS Error Counter */
	uint	txcf;		/* 0x24720 - Transmit Control Frame Counter */
	uint	tovr;		/* 0x24724 - Transmit Oversize Frame Counter */
	uint	tund;		/* 0x24728 - Transmit Undersize Frame Counter */
	uint	tfrg;		/* 0x2472c - Transmit Fragments Frame Counter */
	uint	car1;		/* 0x24730 - Carry Register One */
	uint	car2;		/* 0x24734 - Carry Register Two */
	uint	cam1;		/* 0x24738 - Carry Mask Register One */
	uint	cam2;		/* 0x2473c - Carry Mask Register Two */
	char	res22[192];
	uint	iaddr0;		/* 0x24800 - Indivdual address register 0 */
	uint	iaddr1;		/* 0x24804 - Indivdual address register 1 */
	uint	iaddr2;		/* 0x24808 - Indivdual address register 2 */
	uint	iaddr3;		/* 0x2480c - Indivdual address register 3 */
	uint	iaddr4;		/* 0x24810 - Indivdual address register 4 */
	uint	iaddr5;		/* 0x24814 - Indivdual address register 5 */
	uint	iaddr6;		/* 0x24818 - Indivdual address register 6 */
	uint	iaddr7;		/* 0x2481c - Indivdual address register 7 */
	char	res23[96];
	uint	gaddr0;		/* 0x24880 - Global address register 0 */
	uint	gaddr1;		/* 0x24884 - Global address register 1 */
	uint	gaddr2;		/* 0x24888 - Global address register 2 */
	uint	gaddr3;		/* 0x2488c - Global address register 3 */
	uint	gaddr4;		/* 0x24890 - Global address register 4 */
	uint	gaddr5;		/* 0x24894 - Global address register 5 */
	uint	gaddr6;		/* 0x24898 - Global address register 6 */
	uint	gaddr7;		/* 0x2489c - Global address register 7 */
	char	res24[96];
	uint	pmd0;		/* 0x24900 - Pattern Match Data Register */
	char	res25[4];
	uint	pmask0;		/* 0x24908 - Pattern Mask Register */
	char	res26[4];
	uint	pcntrl0;	/* 0x24910 - Pattern Match Control Register */
	char	res27[4];
	uint	pattrb0;	/* 0x24918 - Pattern Match Attributes Register */
	uint	pattrbeli0;	/* 0x2491c - Pattern Match Attributes Extract Length and Extract Index Register */
	uint	pmd1;		/* 0x24920 - Pattern Match Data Register */
	char	res28[4];
	uint	pmask1;		/* 0x24928 - Pattern Mask Register */
	char	res29[4];
	uint	pcntrl1;	/* 0x24930 - Pattern Match Control Register */
	char	res30[4];
	uint	pattrb1;	/* 0x24938 - Pattern Match Attributes Register */
	uint	pattrbeli1;	/* 0x2493c - Pattern Match Attributes Extract Length and Extract Index Register */
	uint	pmd2;		/* 0x24940 - Pattern Match Data Register */
	char	res31[4];
	uint	pmask2;		/* 0x24948 - Pattern Mask Register */
	char	res32[4];
	uint	pcntrl2;	/* 0x24950 - Pattern Match Control Register */
	char	res33[4];
	uint	pattrb2;	/* 0x24958 - Pattern Match Attributes Register */
	uint	pattrbeli2;	/* 0x2495c - Pattern Match Attributes Extract Length and Extract Index Register */
	uint	pmd3;		/* 0x24960 - Pattern Match Data Register */
	char	res34[4];
	uint	pmask3;		/* 0x24968 - Pattern Mask Register */
	char	res35[4];
	uint	pcntrl3;	/* 0x24970 - Pattern Match Control Register */
	char	res36[4];
	uint	pattrb3;	/* 0x24978 - Pattern Match Attributes Register */
	uint	pattrbeli3;	/* 0x2497c - Pattern Match Attributes Extract Length and Extract Index Register */
	uint	pmd4;		/* 0x24980 - Pattern Match Data Register */
	char	res37[4];
	uint	pmask4;		/* 0x24988 - Pattern Mask Register */
	char	res38[4];
	uint	pcntrl4;	/* 0x24990 - Pattern Match Control Register */
	char	res39[4];
	uint	pattrb4;	/* 0x24998 - Pattern Match Attributes Register */
	uint	pattrbeli4;	/* 0x2499c - Pattern Match Attributes Extract Length and Extract Index Register */
	uint	pmd5;		/* 0x249a0 - Pattern Match Data Register */
	char	res40[4];
	uint	pmask5;		/* 0x249a8 - Pattern Mask Register */
	char	res41[4];
	uint	pcntrl5;	/* 0x249b0 - Pattern Match Control Register */
	char	res42[4];
	uint	pattrb5;	/* 0x249b8 - Pattern Match Attributes Register */
	uint	pattrbeli5;	/* 0x249bc - Pattern Match Attributes Extract Length and Extract Index Register */
	uint	pmd6;		/* 0x249c0 - Pattern Match Data Register */
	char	res43[4];
	uint	pmask6;		/* 0x249c8 - Pattern Mask Register */
	char	res44[4];
	uint	pcntrl6;	/* 0x249d0 - Pattern Match Control Register */
	char	res45[4];
	uint	pattrb6;	/* 0x249d8 - Pattern Match Attributes Register */
	uint	pattrbeli6;	/* 0x249dc - Pattern Match Attributes Extract Length and Extract Index Register */
	uint	pmd7;		/* 0x249e0 - Pattern Match Data Register */
	char	res46[4];
	uint	pmask7;		/* 0x249e8 - Pattern Mask Register */
	char	res47[4];
	uint	pcntrl7;	/* 0x249f0 - Pattern Match Control Register */
	char	res48[4];
	uint	pattrb7;	/* 0x249f8 - Pattern Match Attributes Register */
	uint	pattrbeli7;	/* 0x249fc - Pattern Match Attributes Extract Length and Extract Index Register */
	uint	pmd8;		/* 0x24a00 - Pattern Match Data Register */
	char	res49[4];
	uint	pmask8;		/* 0x24a08 - Pattern Mask Register */
	char	res50[4];
	uint	pcntrl8;	/* 0x24a10 - Pattern Match Control Register */
	char	res51[4];
	uint	pattrb8;	/* 0x24a18 - Pattern Match Attributes Register */
	uint	pattrbeli8;	/* 0x24a1c - Pattern Match Attributes Extract Length and Extract Index Register */
	uint	pmd9;		/* 0x24a20 - Pattern Match Data Register */
	char	res52[4];
	uint	pmask9;		/* 0x24a28 - Pattern Mask Register */
	char	res53[4];
	uint	pcntrl9;	/* 0x24a30 - Pattern Match Control Register */
	char	res54[4];
	uint	pattrb9;	/* 0x24a38 - Pattern Match Attributes Register */
	uint	pattrbeli9;	/* 0x24a3c - Pattern Match Attributes Extract Length and Extract Index Register */
	uint	pmd10;		/* 0x24a40 - Pattern Match Data Register */
	char	res55[4];
	uint	pmask10;	/* 0x24a48 - Pattern Mask Register */
	char	res56[4];