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path: root/source4/libcli/security/security.py
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# This file was automatically generated by SWIG (http://www.swig.org).
# Version 1.3.36
#
# Don't modify this file, modify the SWIG interface instead.

"""
Security-related classes.
"""

import _security
import new
new_instancemethod = new.instancemethod
try:
    _swig_property = property
except NameError:
    pass # Python < 2.2 doesn't have 'property'.
def _swig_setattr_nondynamic(self,class_type,name,value,static=1):
    if (name == "thisown"): return self.this.own(value)
    if (name == "this"):
        if type(value).__name__ == 'PySwigObject':
            self.__dict__[name] = value
            return
    method = class_type.__swig_setmethods__.get(name,None)
    if method: return method(self,value)
    if (not static) or hasattr(self,name):
        self.__dict__[name] = value
    else:
        raise AttributeError("You cannot add attributes to %s" % self)

def _swig_setattr(self,class_type,name,value):
    return _swig_setattr_nondynamic(self,class_type,name,value,0)

def _swig_getattr(self,class_type,name):
    if (name == "thisown"): return self.this.own()
    method = class_type.__swig_getmethods__.get(name,None)
    if method: return method(self)
    raise AttributeError,name

def _swig_repr(self):
    try: strthis = "proxy of " + self.this.__repr__()
    except: strthis = ""
    return "<%s.%s; %s >" % (self.__class__.__module__, self.__class__.__name__, strthis,)

import types
try:
    _object = types.ObjectType
    _newclass = 1
except AttributeError:
    class _object : pass
    _newclass = 0
del types


def _swig_setattr_nondynamic_method(set):
    def set_attr(self,name,value):
        if (name == "thisown"): return self.this.own(value)
        if hasattr(self,name) or (name == "this"):
            set(self,name,value)
        else:
            raise AttributeError("You cannot add attributes to %s" % self)
    return set_attr


SEC_PRIV_SECURITY = _security.SEC_PRIV_SECURITY
SEC_PRIV_BACKUP = _security.SEC_PRIV_BACKUP
SEC_PRIV_RESTORE = _security.SEC_PRIV_RESTORE
SEC_PRIV_SYSTEMTIME = _security.SEC_PRIV_SYSTEMTIME
SEC_PRIV_SHUTDOWN = _security.SEC_PRIV_SHUTDOWN
SEC_PRIV_REMOTE_SHUTDOWN = _security.SEC_PRIV_REMOTE_SHUTDOWN
SEC_PRIV_TAKE_OWNERSHIP = _security.SEC_PRIV_TAKE_OWNERSHIP
SEC_PRIV_DEBUG = _security.SEC_PRIV_DEBUG
SEC_PRIV_SYSTEM_ENVIRONMENT = _security.SEC_PRIV_SYSTEM_ENVIRONMENT
SEC_PRIV_SYSTEM_PROFILE = _security.SEC_PRIV_SYSTEM_PROFILE
SEC_PRIV_PROFILE_SINGLE_PROCESS = _security.SEC_PRIV_PROFILE_SINGLE_PROCESS
SEC_PRIV_INCREASE_BASE_PRIORITY = _security.SEC_PRIV_INCREASE_BASE_PRIORITY
SEC_PRIV_LOAD_DRIVER = _security.SEC_PRIV_LOAD_DRIVER
SEC_PRIV_CREATE_PAGEFILE = _security.SEC_PRIV_CREATE_PAGEFILE
SEC_PRIV_INCREASE_QUOTA = _security.SEC_PRIV_INCREASE_QUOTA
SEC_PRIV_CHANGE_NOTIFY = _security.SEC_PRIV_CHANGE_NOTIFY
SEC_PRIV_UNDOCK = _security.SEC_PRIV_UNDOCK
SEC_PRIV_MANAGE_VOLUME = _security.SEC_PRIV_MANAGE_VOLUME
SEC_PRIV_IMPERSONATE = _security.SEC_PRIV_IMPERSONATE
SEC_PRIV_CREATE_GLOBAL = _security.SEC_PRIV_CREATE_GLOBAL
SEC_PRIV_ENABLE_DELEGATION = _security.SEC_PRIV_ENABLE_DELEGATION
SEC_PRIV_INTERACTIVE_LOGON = _security.SEC_PRIV_INTERACTIVE_LOGON
SEC_PRIV_NETWORK_LOGON = _security.SEC_PRIV_NETWORK_LOGON
SEC_PRIV_REMOTE_INTERACTIVE_LOGON = _security.SEC_PRIV_REMOTE_INTERACTIVE_LOGON
class SecurityToken(object):
    thisown = _swig_property(lambda x: x.this.own(), lambda x, v: x.this.own(v), doc='The membership flag')
    __repr__ = _swig_repr
    def __init__(self, *args, **kwargs): 
        _security.SecurityToken_swiginit(self,_security.new_SecurityToken(*args, **kwargs))
    def is_sid(*args, **kwargs):
        """
        S.is_sid(sid) -> bool
        Check whether this token is of the specified SID.
        """
        return _security.SecurityToken_is_sid(*args, **kwargs)

    def is_system(*args, **kwargs):
        """
        S.is_system() -> bool
        Check whether this is a system token.
        """
        return _security.SecurityToken_is_system(*args, **kwargs)

    def is_anonymous(*args, **kwargs):
        """
        S.is_anonymus() -> bool
        Check whether this is an anonymous token.
        """
        return _security.SecurityToken_is_anonymous(*args, **kwargs)

    __swig_destroy__ = _security.delete_SecurityToken
SecurityToken.is_sid = new_instancemethod(_security.SecurityToken_is_sid,None,SecurityToken)
SecurityToken.is_system = new_instancemethod(_security.SecurityToken_is_system,None,SecurityToken)
SecurityToken.is_anonymous = new_instancemethod(_security.SecurityToken_is_anonymous,None,SecurityToken)
SecurityToken.has_sid = new_instancemethod(_security.SecurityToken_has_sid,None,SecurityToken)
SecurityToken.has_builtin_administrators = new_instancemethod(_security.SecurityToken_has_builtin_administrators,None,SecurityToken)
SecurityToken.has_nt_authenticated_users = new_instancemethod(_security.SecurityToken_has_nt_authenticated_users,None,SecurityToken)
SecurityToken.has_privilege = new_instancemethod(_security.SecurityToken_has_privilege,None,SecurityToken)
SecurityToken.set_privilege = new_instancemethod(_security.SecurityToken_set_privilege,None,SecurityToken)
SecurityToken_swigregister = _security.SecurityToken_swigregister
SecurityToken_swigregister(SecurityToken)

class security_descriptor(object):
    thisown = _swig_property(lambda x: x.this.own(), lambda x, v: x.this.own(v), doc='The membership flag')
    __repr__ = _swig_repr
    def __init__(self, *args, **kwargs): 
        _security.security_descriptor_swiginit(self,_security.new_security_descriptor(*args, **kwargs))
    def sacl_add(*args, **kwargs):
        """
        S.sacl_add(ace) -> None
        Add a security ace to this security descriptor
        """
        return _security.security_descriptor_sacl_add(*args, **kwargs)

    __swig_destroy__ = _security.delete_security_descriptor
security_descriptor.sacl_add = new_instancemethod(_security.security_descriptor_sacl_add,None,security_descriptor)
security_descriptor.dacl_add = new_instancemethod(_security.security_descriptor_dacl_add,None,security_descriptor)
security_descriptor.dacl_del = new_instancemethod(_security.security_descriptor_dacl_del,None,security_descriptor)
security_descriptor.sacl_del = new_instancemethod(_security.security_descriptor_sacl_del,None,security_descriptor)
security_descriptor.__eq__ = new_instancemethod(_security.security_descriptor___eq__,None,security_descriptor)
security_descriptor_swigregister = _security.security_descriptor_swigregister
security_descriptor_swigregister(security_descriptor)

class Sid(object):
    thisown = _swig_property(lambda x: x.this.own(), lambda x, v: x.this.own(v), doc='The membership flag')
    __repr__ = _swig_repr
    sid_rev_num = _swig_property(_security.Sid_sid_rev_num_get)
    num_auths = _swig_property(_security.Sid_num_auths_get)
    id_auth = _swig_property(_security.Sid_id_auth_get)
    sub_auths = _swig_property(_security.Sid_sub_auths_get)
    def __init__(self, *args, **kwargs): 
        _security.Sid_swiginit(self,_security.new_Sid(*args, **kwargs))
    def __repr__(self):
        return "Sid(%r)" % str(self)

    __swig_destroy__ = _security.delete_Sid
Sid.__str__ = new_instancemethod(_security.Sid___str__,None,Sid)
Sid.__eq__ = new_instancemethod(_security.Sid___eq__,None,Sid)
Sid_swigregister = _security.Sid_swigregister
Sid_swigregister(Sid)


def random_sid(*args):
  """
    random_sid() -> sid
    Generate a random SID
    """
  return _security.random_sid(*args)
privilege_name = _security.privilege_name
privilege_id = _security.privilege_id


hl opt">, seq[qn_output[i]][0]); else gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); udelay(500); gpio_direction_output(IOX_SHCP, 1); udelay(500); } gpio_direction_output(IOX_STCP, 0); udelay(500); /* * shift register will be output to pins */ gpio_direction_output(IOX_STCP, 1); for (i = 7; i >= 0; i--) { gpio_direction_output(IOX_SHCP, 0); gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); udelay(500); gpio_direction_output(IOX_SHCP, 1); udelay(500); } gpio_direction_output(IOX_STCP, 0); udelay(500); /* * shift register will be output to pins */ gpio_direction_output(IOX_STCP, 1); gpio_direction_output(IOX_OE, 1); }; #ifdef CONFIG_SYS_I2C_MXC #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) /* I2C1 for PMIC and EEPROM */ struct i2c_pads_info i2c_pad_info1 = { .scl = { .i2c_mode = MX6_PAD_UART4_TX_DATA__I2C1_SCL | PC, .gpio_mode = MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | PC, .gp = IMX_GPIO_NR(1, 28), }, .sda = { .i2c_mode = MX6_PAD_UART4_RX_DATA__I2C1_SDA | PC, .gpio_mode = MX6_PAD_UART4_RX_DATA__GPIO1_IO29 | PC, .gp = IMX_GPIO_NR(1, 29), }, }; #endif int dram_init(void) { gd->ram_size = PHYS_SDRAM_SIZE; return 0; } static iomux_v3_cfg_t const uart1_pads[] = { MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), }; static iomux_v3_cfg_t const usdhc1_pads[] = { MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* VSELECT */ MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* CD */ MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), /* RST_B */ MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), }; /* * mx6ul_14x14_evk board default supports sd card. If want to use * EMMC, need to do board rework for sd2. * Introduce CONFIG_MX6UL_14X14_EVK_EMMC_REWORK, if sd2 reworked to support * emmc, need to define this macro. */ #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK) static iomux_v3_cfg_t const usdhc2_emmc_pads[] = { MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* * RST_B */ MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), }; #else static iomux_v3_cfg_t const usdhc2_pads[] = { MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), }; static iomux_v3_cfg_t const usdhc2_cd_pads[] = { /* * The evk board uses DAT3 to detect CD card plugin, * in u-boot we mux the pin to GPIO when doing board_mmc_getcd. */ MX6_PAD_NAND_DATA03__GPIO4_IO05 | MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL), }; static iomux_v3_cfg_t const usdhc2_dat3_pads[] = { MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL), }; #endif static void setup_iomux_uart(void) { imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); } #ifdef CONFIG_FSL_QSPI #define QSPI_PAD_CTRL1 \ (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \ PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_60ohm) static iomux_v3_cfg_t const quadspi_pads[] = { MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), MX6_PAD_NAND_READY_B__QSPI_A_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), MX6_PAD_NAND_CLE__QSPI_A_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), }; int board_qspi_init(void) { /* Set the iomux */ imx_iomux_v3_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads)); /* Set the clock */ enable_qspi_clk(0); return 0; } #endif #ifdef CONFIG_FSL_ESDHC static struct fsl_esdhc_cfg usdhc_cfg[2] = { {USDHC1_BASE_ADDR, 0, 4}, #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK) {USDHC2_BASE_ADDR, 0, 8}, #else {USDHC2_BASE_ADDR, 0, 4}, #endif }; #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19) #define USDHC1_PWR_GPIO IMX_GPIO_NR(1, 9) #define USDHC2_CD_GPIO IMX_GPIO_NR(4, 5) #define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10) int board_mmc_getcd(struct mmc *mmc) { struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; int ret = 0; switch (cfg->esdhc_base) { case USDHC1_BASE_ADDR: ret = !gpio_get_value(USDHC1_CD_GPIO); break; case USDHC2_BASE_ADDR: #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK) ret = 1; #else imx_iomux_v3_setup_multiple_pads(usdhc2_cd_pads, ARRAY_SIZE(usdhc2_cd_pads)); gpio_direction_input(USDHC2_CD_GPIO); /* * Since it is the DAT3 pin, this pin is pulled to * low voltage if no card */ ret = gpio_get_value(USDHC2_CD_GPIO); imx_iomux_v3_setup_multiple_pads(usdhc2_dat3_pads, ARRAY_SIZE(usdhc2_dat3_pads)); #endif break; } return ret; } int board_mmc_init(bd_t *bis) { #ifdef CONFIG_SPL_BUILD #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK) imx_iomux_v3_setup_multiple_pads(usdhc2_emmc_pads, ARRAY_SIZE(usdhc2_emmc_pads)); #else imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); #endif gpio_direction_output(USDHC2_PWR_GPIO, 0); udelay(500); gpio_direction_output(USDHC2_PWR_GPIO, 1); usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); return fsl_esdhc_initialize(bis, &usdhc_cfg[1]); #else int i, ret; /* * According to the board_mmc_init() the following map is done: * (U-boot device node) (Physical Port) * mmc0 USDHC1 * mmc1 USDHC2 */ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { switch (i) { case 0: imx_iomux_v3_setup_multiple_pads( usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); gpio_direction_input(USDHC1_CD_GPIO); usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); gpio_direction_output(USDHC1_PWR_GPIO, 0); udelay(500); gpio_direction_output(USDHC1_PWR_GPIO, 1); break; case 1: #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK) imx_iomux_v3_setup_multiple_pads( usdhc2_emmc_pads, ARRAY_SIZE(usdhc2_emmc_pads)); #else imx_iomux_v3_setup_multiple_pads( usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); #endif gpio_direction_output(USDHC2_PWR_GPIO, 0); udelay(500); gpio_direction_output(USDHC2_PWR_GPIO, 1); usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); break; default: printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", i + 1); return -EINVAL; } ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); if (ret) { printf("Warning: failed to initialize mmc dev %d\n", i); return ret; } } #endif return 0; } #endif #ifdef CONFIG_USB_EHCI_MX6 #define USB_OTHERREGS_OFFSET 0x800 #define UCTRL_PWR_POL (1 << 9) static iomux_v3_cfg_t const usb_otg_pads[] = { MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL), }; /* At default the 3v3 enables the MIC2026 for VBUS power */ static void setup_usb(void) { imx_iomux_v3_setup_multiple_pads(usb_otg_pads, ARRAY_SIZE(usb_otg_pads)); } int board_usb_phy_mode(int port) { if (port == 1) return USB_INIT_HOST; else return usb_phy_mode(port); } int board_ehci_hcd_init(int port) { u32 *usbnc_usb_ctrl; if (port > 1) return -EINVAL; usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + port * 4); /* Set Power polarity */ setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); return 0; } #endif int board_early_init_f(void) { setup_iomux_uart(); return 0; } int board_init(void) { /* Address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads));