diff options
Diffstat (limited to 'drivers/block/DAC960.h')
| -rw-r--r-- | drivers/block/DAC960.h | 317 |
1 files changed, 316 insertions, 1 deletions
diff --git a/drivers/block/DAC960.h b/drivers/block/DAC960.h index d5e8e7190c9..a82f37f749a 100644 --- a/drivers/block/DAC960.h +++ b/drivers/block/DAC960.h @@ -2114,7 +2114,8 @@ typedef enum DAC960_LA_Controller = 3, /* DAC1164P */ DAC960_PG_Controller = 4, /* DAC960PTL/PJ/PG */ DAC960_PD_Controller = 5, /* DAC960PU/PD/PL/P */ - DAC960_P_Controller = 6 /* DAC960PU/PD/PL/P */ + DAC960_P_Controller = 6, /* DAC960PU/PD/PL/P */ + DAC960_GEM_Controller = 7, /* AcceleRAID 4/5/600 */ } DAC960_HardwareType_T; @@ -2541,6 +2542,320 @@ void dma_addr_writeql(dma_addr_t addr, void __iomem *write_address) } /* + Define the DAC960 GEM Series Controller Interface Register Offsets. + */ + +#define DAC960_GEM_RegisterWindowSize 0x600 + +typedef enum +{ + DAC960_GEM_InboundDoorBellRegisterReadSetOffset = 0x214, + DAC960_GEM_InboundDoorBellRegisterClearOffset = 0x218, + DAC960_GEM_OutboundDoorBellRegisterReadSetOffset = 0x224, + DAC960_GEM_OutboundDoorBellRegisterClearOffset = 0x228, + DAC960_GEM_InterruptStatusRegisterOffset = 0x208, + DAC960_GEM_InterruptMaskRegisterReadSetOffset = 0x22C, + DAC960_GEM_InterruptMaskRegisterClearOffset = 0x230, + DAC960_GEM_CommandMailboxBusAddressOffset = 0x510, + DAC960_GEM_CommandStatusOffset = 0x518, + DAC960_GEM_ErrorStatusRegisterReadSetOffset = 0x224, + DAC960_GEM_ErrorStatusRegisterClearOffset = 0x228, +} +DAC960_GEM_RegisterOffsets_T; + +/* + Define the structure of the DAC960 GEM Series Inbound Door Bell + */ + +typedef union DAC960_GEM_InboundDoorBellRegister +{ + unsigned int All; + struct { + unsigned int :24; + boolean HardwareMailboxNewCommand:1; + boolean AcknowledgeHardwareMailboxStatus:1; + boolean GenerateInterrupt:1; + boolean ControllerReset:1; + boolean MemoryMailboxNewCommand:1; + unsigned int :3; + } Write; + struct { + unsigned int :24; + boolean HardwareMailboxFull:1; + boolean InitializationInProgress:1; + unsigned int :6; + } Read; +} +DAC960_GEM_InboundDoorBellRegister_T; + +/* + Define the structure of the DAC960 GEM Series Outbound Door Bell Register. + */ +typedef union DAC960_GEM_OutboundDoorBellRegister +{ + unsigned int All; + struct { + unsigned int :24; + boolean AcknowledgeHardwareMailboxInterrupt:1; + boolean AcknowledgeMemoryMailboxInterrupt:1; + unsigned int :6; + } Write; + struct { + unsigned int :24; + boolean HardwareMailboxStatusAvailable:1; + boolean MemoryMailboxStatusAvailable:1; + unsigned int :6; + } Read; +} +DAC960_GEM_OutboundDoorBellRegister_T; + +/* + Define the structure of the DAC960 GEM Series Interrupt Mask Register. + */ +typedef union DAC960_GEM_InterruptMaskRegister +{ + unsigned int All; + struct { + unsigned int :16; + unsigned int :8; + unsigned int HardwareMailboxInterrupt:1; + unsigned int MemoryMailboxInterrupt:1; + unsigned int :6; + } Bits; +} +DAC960_GEM_InterruptMaskRegister_T; + +/* + Define the structure of the DAC960 GEM Series Error Status Register. + */ + +typedef union DAC960_GEM_ErrorStatusRegister +{ + unsigned int All; + struct { + unsigned int :24; + unsigned int :5; + boolean ErrorStatusPending:1; + unsigned int :2; + } Bits; +} +DAC960_GEM_ErrorStatusRegister_T; + +/* + Define inline functions to provide an abstraction for reading and writing the + DAC960 GEM Series Controller Interface Registers. +*/ + +static inline +void DAC960_GEM_HardwareMailboxNewCommand(void __iomem *ControllerBaseAddress) +{ + DAC960_GEM_InboundDoorBellRegister_T InboundDoorBellRegister; + InboundDoorBellRegister.All = 0; + InboundDoorBellRegister.Write.HardwareMailboxNewCommand = true; + writel(InboundDoorBellRegister.All, + ControllerBaseAddress + DAC960_GEM_InboundDoorBellRegisterReadSetOffset); +} + +static inline +void DAC960_GEM_AcknowledgeHardwareMailboxStatus(void __iomem *ControllerBaseAddress) +{ + DAC960_GEM_InboundDoorBellRegister_T InboundDoorBellRegister; + InboundDoorBellRegister.All = 0; + InboundDoorBellRegister.Write.AcknowledgeHardwareMailboxStatus = true; + writel(InboundDoorBellRegister.All, + ControllerBaseAddress + DAC960_GEM_InboundDoorBellRegisterClearOffset); +} + +static inline +void DAC960_GEM_GenerateInterrupt(void __iomem *ControllerBaseAddress) +{ + DAC960_GEM_InboundDoorBellRegister_T InboundDoorBellRegister; + InboundDoorBellRegister.All = 0; + InboundDoorBellRegister.Write.GenerateInterrupt = true; + writel(InboundDoorBellRegister.All, + ControllerBaseAddress + DAC960_GEM_InboundDoorBellRegisterReadSetOffset); +} + +static inline +void DAC960_GEM_ControllerReset(void __iomem *ControllerBaseAddress) +{ + DAC960_GEM_InboundDoorBellRegister_T InboundDoorBellRegister; + InboundDoorBellRegister.All = 0; + InboundDoorBellRegister.Write.ControllerReset = true; + writel(InboundDoorBellRegister.All, + ControllerBaseAddress + DAC960_GEM_InboundDoorBellRegisterReadSetOffset); +} + +static inline +void DAC960_GEM_MemoryMailboxNewCommand(void __iomem *ControllerBaseAddress) +{ + DAC960_GEM_InboundDoorBellRegister_T InboundDoorBellRegister; + InboundDoorBellRegister.All = 0; + InboundDoorBellRegister.Write.MemoryMailboxNewCommand = true; + writel(InboundDoorBellRegister.All, + ControllerBaseAddress + DAC960_GEM_InboundDoorBellRegisterReadSetOffset); +} + +static inline +boolean DAC960_GEM_HardwareMailboxFullP(void __iomem *ControllerBaseAddress) +{ + DAC960_GEM_InboundDoorBellRegister_T InboundDoorBellRegister; + InboundDoorBellRegister.All = + readl(ControllerBaseAddress + + DAC960_GEM_InboundDoorBellRegisterReadSetOffset); + return InboundDoorBellRegister.Read.HardwareMailboxFull; +} + +static inline +boolean DAC960_GEM_InitializationInProgressP(void __iomem *ControllerBaseAddress) +{ + DAC960_GEM_InboundDoorBellRegister_T InboundDoorBellRegister; + InboundDoorBellRegister.All = + readl(ControllerBaseAddress + + DAC960_GEM_InboundDoorBellRegisterReadSetOffset); + return InboundDoorBellRegister.Read.InitializationInProgress; +} + +static inline +void DAC960_GEM_AcknowledgeHardwareMailboxInterrupt(void __iomem *ControllerBaseAddress) +{ + DAC960_GEM_OutboundDoorBellRegister_T OutboundDoorBellRegister; + OutboundDoorBellRegister.All = 0; + OutboundDoorBellRegister.Write.AcknowledgeHardwareMailboxInterrupt = true; + writel(OutboundDoorBellRegister.All, + ControllerBaseAddress + DAC960_GEM_OutboundDoorBellRegisterClearOffset); +} + +static inline +void DAC960_GEM_AcknowledgeMemoryMailboxInterrupt(void __iomem *ControllerBaseAddress) +{ + DAC960_GEM_OutboundDoorBellRegister_T OutboundDoorBellRegister; + OutboundDoorBellRegister.All = 0; + OutboundDoorBellRegister.Write.AcknowledgeMemoryMailboxInterrupt = true; + writel(OutboundDoorBellRegister.All, + ControllerBaseAddress + DAC960_GEM_OutboundDoorBellRegisterClearOffset); +} + +static inline +void DAC960_GEM_AcknowledgeInterrupt(void __iomem *ControllerBaseAddress) +{ + DAC960_GEM_OutboundDoorBellRegister_T OutboundDoorBellRegister; + OutboundDoorBellRegister.All = 0; + OutboundDoorBellRegister.Write.AcknowledgeHardwareMailboxInterrupt = true; + OutboundDoorBellRegister.Write.AcknowledgeMemoryMailboxInterrupt = true; + writel(OutboundDoorBellRegister.All, + ControllerBaseAddress + DAC960_GEM_OutboundDoorBellRegisterClearOffset); +} + +static inline +boolean DAC960_GEM_HardwareMailboxStatusAvailableP(void __iomem *ControllerBaseAddress) +{ + DAC960_GEM_OutboundDoorBellRegister_T OutboundDoorBellRegister; + OutboundDoorBellRegister.All = + readl(ControllerBaseAddress + + DAC960_GEM_OutboundDoorBellRegisterReadSetOffset); + return OutboundDoorBellRegister.Read.HardwareMailboxStatusAvailable; +} + +static inline +boolean DAC960_GEM_MemoryMailboxStatusAvailableP(void __iomem *ControllerBaseAddress) +{ + DAC960_GEM_OutboundDoorBellRegister_T OutboundDoorBellRegister; + OutboundDoorBellRegister.All = + readl(ControllerBaseAddress + + DAC960_GEM_OutboundDoorBellRegisterReadSetOffset); + return OutboundDoorBellRegister.Read.MemoryMailboxStatusAvailable; +} + +static inline +void DAC960_GEM_EnableInterrupts(void __iomem *ControllerBaseAddress) +{ + DAC960_GEM_InterruptMaskRegister_T InterruptMaskRegister; + InterruptMaskRegister.All = 0; + InterruptMaskRegister.Bits.HardwareMailboxInterrupt = true; + InterruptMaskRegister.Bits.MemoryMailboxInterrupt = true; + writel(InterruptMaskRegister.All, + ControllerBaseAddress + DAC960_GEM_InterruptMaskRegisterClearOffset); +} + +static inline +void DAC960_GEM_DisableInterrupts(void __iomem *ControllerBaseAddress) +{ + DAC960_GEM_InterruptMaskRegister_T InterruptMaskRegister; + InterruptMaskRegister.All = 0; + InterruptMaskRegister.Bits.HardwareMailboxInterrupt = true; + InterruptMaskRegister.Bits.MemoryMailboxInterrupt = true; + writel(InterruptMaskRegister.All, + ControllerBaseAddress + DAC960_GEM_InterruptMaskRegisterReadSetOffset); +} + +static inline +boolean DAC960_GEM_InterruptsEnabledP(void __iomem *ControllerBaseAddress) +{ + DAC960_GEM_InterruptMaskRegister_T InterruptMaskRegister; + InterruptMaskRegister.All = + readl(ControllerBaseAddress + + DAC960_GEM_InterruptMaskRegisterReadSetOffset); + return !(InterruptMaskRegister.Bits.HardwareMailboxInterrupt || + InterruptMaskRegister.Bits.MemoryMailboxInterrupt); +} + +static inline +void DAC960_GEM_WriteCommandMailbox(DAC960_V2_CommandMailbox_T + *MemoryCommandMailbox, + DAC960_V2_CommandMailbox_T + *CommandMailbox) +{ + memcpy(&MemoryCommandMailbox->Words[1], &CommandMailbox->Words[1], + sizeof(DAC960_V2_CommandMailbox_T) - sizeof(unsigned int)); + wmb(); + MemoryCommandMailbox->Words[0] = CommandMailbox->Words[0]; + mb(); +} + +static inline +void DAC960_GEM_WriteHardwareMailbox(void __iomem *ControllerBaseAddress, + dma_addr_t CommandMailboxDMA) +{ + dma_addr_writeql(CommandMailboxDMA, + ControllerBaseAddress + + DAC960_GEM_CommandMailboxBusAddressOffset); +} + +static inline DAC960_V2_CommandIdentifier_T +DAC960_GEM_ReadCommandIdentifier(void __iomem *ControllerBaseAddress) +{ + return readw(ControllerBaseAddress + DAC960_GEM_CommandStatusOffset); +} + +static inline DAC960_V2_CommandStatus_T +DAC960_GEM_ReadCommandStatus(void __iomem *ControllerBaseAddress) +{ + return readw(ControllerBaseAddress + DAC960_GEM_CommandStatusOffset + 2); +} + +static inline boolean +DAC960_GEM_ReadErrorStatus(void __iomem *ControllerBaseAddress, + unsigned char *ErrorStatus, + unsigned char *Parameter0, + unsigned char *Parameter1) +{ + DAC960_GEM_ErrorStatusRegister_T ErrorStatusRegister; + ErrorStatusRegister.All = + readl(ControllerBaseAddress + DAC960_GEM_ErrorStatusRegisterReadSetOffset); + if (!ErrorStatusRegister.Bits.ErrorStatusPending) return false; + ErrorStatusRegister.Bits.ErrorStatusPending = false; + *ErrorStatus = ErrorStatusRegister.All; + *Parameter0 = + readb(ControllerBaseAddress + DAC960_GEM_CommandMailboxBusAddressOffset + 0); + *Parameter1 = + readb(ControllerBaseAddress + DAC960_GEM_CommandMailboxBusAddressOffset + 1); + writel(0x03000000, ControllerBaseAddress + + DAC960_GEM_ErrorStatusRegisterClearOffset); + return true; +} + +/* Define the DAC960 BA Series Controller Interface Register Offsets. */ |