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-rw-r--r--arch/sparc64/kernel/devices.c2
-rw-r--r--arch/sparc64/kernel/entry.S13
-rw-r--r--arch/sparc64/kernel/irq.c1016
-rw-r--r--arch/sparc64/kernel/pci.c38
-rw-r--r--arch/sparc64/kernel/pci_psycho.c81
-rw-r--r--arch/sparc64/kernel/pci_sabre.c99
-rw-r--r--arch/sparc64/kernel/pci_schizo.c192
-rw-r--r--arch/sparc64/kernel/pci_sun4v.c32
-rw-r--r--arch/sparc64/kernel/sbus.c47
-rw-r--r--arch/sparc64/kernel/sparc64_ksyms.c7
-rw-r--r--arch/sparc64/kernel/sun4v_ivec.S15
-rw-r--r--arch/sparc64/kernel/time.c16
-rw-r--r--arch/sparc64/kernel/traps.c4
-rw-r--r--arch/sparc64/kernel/ttable.S10
14 files changed, 422 insertions, 1150 deletions
diff --git a/arch/sparc64/kernel/devices.c b/arch/sparc64/kernel/devices.c
index 007e8922cd1..0dd95ae50e1 100644
--- a/arch/sparc64/kernel/devices.c
+++ b/arch/sparc64/kernel/devices.c
@@ -157,7 +157,7 @@ unsigned int sun4v_vdev_device_interrupt(unsigned int dev_node)
return 0;
}
- return sun4v_build_irq(sun4v_vdev_devhandle, irq, 5, 0);
+ return sun4v_build_irq(sun4v_vdev_devhandle, irq);
}
static const char *cpu_mid_prop(void)
diff --git a/arch/sparc64/kernel/entry.S b/arch/sparc64/kernel/entry.S
index 6d0b3ed77a0..be85ce2a4ad 100644
--- a/arch/sparc64/kernel/entry.S
+++ b/arch/sparc64/kernel/entry.S
@@ -22,6 +22,7 @@
#include <asm/estate.h>
#include <asm/auxio.h>
#include <asm/sfafsr.h>
+#include <asm/pil.h>
#define curptr g6
@@ -431,20 +432,16 @@ do_ivec:
membar #Sync
sethi %hi(ivector_table), %g2
- sllx %g3, 5, %g3
+ sllx %g3, 3, %g3
or %g2, %lo(ivector_table), %g2
add %g2, %g3, %g3
- ldub [%g3 + 0x04], %g4 /* pil */
- mov 1, %g2
- sllx %g2, %g4, %g2
- sllx %g4, 2, %g4
TRAP_LOAD_IRQ_WORK(%g6, %g1)
- lduw [%g6 + %g4], %g5 /* g5 = irq_work(cpu, pil) */
+ lduw [%g6], %g5 /* g5 = irq_work(cpu) */
stw %g5, [%g3 + 0x00] /* bucket->irq_chain = g5 */
- stw %g3, [%g6 + %g4] /* irq_work(cpu, pil) = bucket */
- wr %g2, 0x0, %set_softint
+ stw %g3, [%g6] /* irq_work(cpu) = bucket */
+ wr %g0, 1 << PIL_DEVICE_IRQ, %set_softint
retry
do_ivec_xcall:
mov 0x50, %g1
diff --git a/arch/sparc64/kernel/irq.c b/arch/sparc64/kernel/irq.c
index 11e645c9ec5..a8c9dc8d195 100644
--- a/arch/sparc64/kernel/irq.c
+++ b/arch/sparc64/kernel/irq.c
@@ -22,6 +22,7 @@
#include <linux/proc_fs.h>
#include <linux/seq_file.h>
#include <linux/bootmem.h>
+#include <linux/irq.h>
#include <asm/ptrace.h>
#include <asm/processor.h>
@@ -42,10 +43,6 @@
#include <asm/auxio.h>
#include <asm/head.h>
-#ifdef CONFIG_SMP
-static void distribute_irqs(void);
-#endif
-
/* UPA nodes send interrupt packet to UltraSparc with first data reg
* value low 5 (7 on Starfire) bits holding the IRQ identifier being
* delivered. We must translate this into a non-vector IRQ so we can
@@ -57,10 +54,29 @@ static void distribute_irqs(void);
* The IVEC handler does not need to act atomically, the PIL dispatch
* code uses CAS to get an atomic snapshot of the list and clear it
* at the same time.
+ *
+ * If you make changes to ino_bucket, please update hand coded assembler
+ * of the vectored interrupt trap handler(s) in entry.S and sun4v_ivec.S
*/
+struct ino_bucket {
+ /* Next handler in per-CPU IRQ worklist. We know that
+ * bucket pointers have the high 32-bits clear, so to
+ * save space we only store the bits we need.
+ */
+/*0x00*/unsigned int irq_chain;
+ /* Virtual interrupt number assigned to this INO. */
+/*0x04*/unsigned int virt_irq;
+};
+
+#define NUM_IVECS (IMAP_INR + 1)
struct ino_bucket ivector_table[NUM_IVECS] __attribute__ ((aligned (SMP_CACHE_BYTES)));
+#define __irq_ino(irq) \
+ (((struct ino_bucket *)(unsigned long)(irq)) - &ivector_table[0])
+#define __bucket(irq) ((struct ino_bucket *)(unsigned long)(irq))
+#define __irq(bucket) ((unsigned int)(unsigned long)(bucket))
+
/* This has to be in the main kernel image, it cannot be
* turned into per-cpu data. The reason is that the main
* kernel image is locked into the TLB and this structure
@@ -68,71 +84,82 @@ struct ino_bucket ivector_table[NUM_IVECS] __attribute__ ((aligned (SMP_CACHE_BY
* access to this structure takes a TLB miss it could cause
* the 5-level sparc v9 trap stack to overflow.
*/
-struct irq_work_struct {
- unsigned int irq_worklists[16];
-};
-struct irq_work_struct __irq_work[NR_CPUS];
-#define irq_work(__cpu, __pil) &(__irq_work[(__cpu)].irq_worklists[(__pil)])
+#define irq_work(__cpu) &(trap_block[(__cpu)].irq_worklist)
-static struct irqaction *irq_action[NR_IRQS+1];
+static unsigned int virt_to_real_irq_table[NR_IRQS];
+static unsigned char virt_irq_cur = 1;
-/* This only synchronizes entities which modify IRQ handler
- * state and some selected user-level spots that want to
- * read things in the table. IRQ handler processing orders
- * its' accesses such that no locking is needed.
- */
-static DEFINE_SPINLOCK(irq_action_lock);
+static unsigned char virt_irq_alloc(unsigned int real_irq)
+{
+ unsigned char ent;
+
+ BUILD_BUG_ON(NR_IRQS >= 256);
+
+ ent = virt_irq_cur;
+ if (ent >= NR_IRQS) {
+ printk(KERN_ERR "IRQ: Out of virtual IRQs.\n");
+ return 0;
+ }
+
+ virt_irq_cur = ent + 1;
+ virt_to_real_irq_table[ent] = real_irq;
+
+ return ent;
+}
+
+#if 0 /* Currently unused. */
+static unsigned char real_to_virt_irq(unsigned int real_irq)
+{
+ struct ino_bucket *bucket = __bucket(real_irq);
-static void register_irq_proc (unsigned int irq);
+ return bucket->virt_irq;
+}
+#endif
+
+static unsigned int virt_to_real_irq(unsigned char virt_irq)
+{
+ return virt_to_real_irq_table[virt_irq];
+}
/*
- * Upper 2b of irqaction->flags holds the ino.
- * irqaction->mask holds the smp affinity information.
+ * /proc/interrupts printing:
*/
-#define put_ino_in_irqaction(action, irq) \
- action->flags &= 0xffffffffffffUL; \
- if (__bucket(irq) == &pil0_dummy_bucket) \
- action->flags |= 0xdeadUL << 48; \
- else \
- action->flags |= __irq_ino(irq) << 48;
-#define get_ino_in_irqaction(action) (action->flags >> 48)
-
-#define put_smpaff_in_irqaction(action, smpaff) (action)->mask = (smpaff)
-#define get_smpaff_in_irqaction(action) ((action)->mask)
int show_interrupts(struct seq_file *p, void *v)
{
+ int i = *(loff_t *) v, j;
+ struct irqaction * action;
unsigned long flags;
- int i = *(loff_t *) v;
- struct irqaction *action;
-#ifdef CONFIG_SMP
- int j;
-#endif
- spin_lock_irqsave(&irq_action_lock, flags);
- if (i <= NR_IRQS) {
- if (!(action = *(i + irq_action)))
- goto out_unlock;
- seq_printf(p, "%3d: ", i);
+ if (i == 0) {
+ seq_printf(p, " ");
+ for_each_online_cpu(j)
+ seq_printf(p, "CPU%d ",j);
+ seq_putc(p, '\n');
+ }
+
+ if (i < NR_IRQS) {
+ spin_lock_irqsave(&irq_desc[i].lock, flags);
+ action = irq_desc[i].action;
+ if (!action)
+ goto skip;
+ seq_printf(p, "%3d: ",i);
#ifndef CONFIG_SMP
seq_printf(p, "%10u ", kstat_irqs(i));
#else
- for_each_online_cpu(j) {
- seq_printf(p, "%10u ",
- kstat_cpu(j).irqs[i]);
- }
+ for_each_online_cpu(j)
+ seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
#endif
- seq_printf(p, " %s:%lx", action->name,
- get_ino_in_irqaction(action));
- for (action = action->next; action; action = action->next) {
- seq_printf(p, ", %s:%lx", action->name,
- get_ino_in_irqaction(action));
- }
+ seq_printf(p, " %9s", irq_desc[i].handler->typename);
+ seq_printf(p, " %s", action->name);
+
+ for (action=action->next; action; action = action->next)
+ seq_printf(p, ", %s", action->name);
+
seq_putc(p, '\n');
+skip:
+ spin_unlock_irqrestore(&irq_desc[i].lock, flags);
}
-out_unlock:
- spin_unlock_irqrestore(&irq_action_lock, flags);
-
return 0;
}
@@ -173,556 +200,365 @@ static unsigned int sun4u_compute_tid(unsigned long imap, unsigned long cpuid)
return tid;
}
-/* Now these are always passed a true fully specified sun4u INO. */
-void enable_irq(unsigned int irq)
-{
- struct ino_bucket *bucket = __bucket(irq);
- unsigned long imap, cpuid;
-
- imap = bucket->imap;
- if (imap == 0UL)
- return;
-
- preempt_disable();
-
- /* This gets the physical processor ID, even on uniprocessor,
- * so we can always program the interrupt target correctly.
- */
- cpuid = real_hard_smp_processor_id();
-
- if (tlb_type == hypervisor) {
- unsigned int ino = __irq_ino(irq);
- int err;
+struct irq_handler_data {
+ unsigned long iclr;
+ unsigned long imap;
- err = sun4v_intr_settarget(ino, cpuid);
- if (err != HV_EOK)
- printk("sun4v_intr_settarget(%x,%lu): err(%d)\n",
- ino, cpuid, err);
- err = sun4v_intr_setenabled(ino, HV_INTR_ENABLED);
- if (err != HV_EOK)
- printk("sun4v_intr_setenabled(%x): err(%d)\n",
- ino, err);
- } else {
- unsigned int tid = sun4u_compute_tid(imap, cpuid);
-
- /* NOTE NOTE NOTE, IGN and INO are read-only, IGN is a product
- * of this SYSIO's preconfigured IGN in the SYSIO Control
- * Register, the hardware just mirrors that value here.
- * However for Graphics and UPA Slave devices the full
- * IMAP_INR field can be set by the programmer here.
- *
- * Things like FFB can now be handled via the new IRQ
- * mechanism.
- */
- upa_writel(tid | IMAP_VALID, imap);
- }
-
- preempt_enable();
-}
+ void (*pre_handler)(unsigned int, void *, void *);
+ void *pre_handler_arg1;
+ void *pre_handler_arg2;
+};
-/* This now gets passed true ino's as well. */
-void disable_irq(unsigned int irq)
+static inline struct ino_bucket *virt_irq_to_bucket(unsigned int virt_irq)
{
- struct ino_bucket *bucket = __bucket(irq);
- unsigned long imap;
-
- imap = bucket->imap;
- if (imap != 0UL) {
- if (tlb_type == hypervisor) {
- unsigned int ino = __irq_ino(irq);
- int err;
-
- err = sun4v_intr_setenabled(ino, HV_INTR_DISABLED);
- if (err != HV_EOK)
- printk("sun4v_intr_setenabled(%x): "
- "err(%d)\n", ino, err);
- } else {
- u32 tmp;
-
- /* NOTE: We do not want to futz with the IRQ clear registers
- * and move the state to IDLE, the SCSI code does call
- * disable_irq() to assure atomicity in the queue cmd
- * SCSI adapter driver code. Thus we'd lose interrupts.
- */
- tmp = upa_readl(imap);
- tmp &= ~IMAP_VALID;
- upa_writel(tmp, imap);
- }
- }
-}
+ unsigned int real_irq = virt_to_real_irq(virt_irq);
+ struct ino_bucket *bucket = NULL;
-/* The timer is the one "weird" interrupt which is generated by
- * the CPU %tick register and not by some normal vectored interrupt
- * source. To handle this special case, we use this dummy INO bucket.
- */
-static struct irq_desc pil0_dummy_desc;
-static struct ino_bucket pil0_dummy_bucket = {
- .irq_info = &pil0_dummy_desc,
-};
+ if (likely(real_irq))
+ bucket = __bucket(real_irq);
-static void build_irq_error(const char *msg, unsigned int ino, int pil, int inofixup,
- unsigned long iclr, unsigned long imap,
- struct ino_bucket *bucket)
-{
- prom_printf("IRQ: INO %04x (%d:%016lx:%016lx) --> "
- "(%d:%d:%016lx:%016lx), halting...\n",
- ino, bucket->pil, bucket->iclr, bucket->imap,
- pil, inofixup, iclr, imap);
- prom_halt();
+ return bucket;
}
-unsigned int build_irq(int pil, int inofixup, unsigned long iclr, unsigned long imap)
+#ifdef CONFIG_SMP
+static int irq_choose_cpu(unsigned int virt_irq)
{
- struct ino_bucket *bucket;
- int ino;
+ cpumask_t mask = irq_affinity[virt_irq];
+ int cpuid;
- if (pil == 0) {
- if (iclr != 0UL || imap != 0UL) {
- prom_printf("Invalid dummy bucket for PIL0 (%lx:%lx)\n",
- iclr, imap);
- prom_halt();
- }
- return __irq(&pil0_dummy_bucket);
- }
+ if (cpus_equal(mask, CPU_MASK_ALL)) {
+ static int irq_rover;
+ static DEFINE_SPINLOCK(irq_rover_lock);
+ unsigned long flags;
- BUG_ON(tlb_type == hypervisor);
+ /* Round-robin distribution... */
+ do_round_robin:
+ spin_lock_irqsave(&irq_rover_lock, flags);
- /* RULE: Both must be specified in all other cases. */
- if (iclr == 0UL || imap == 0UL) {
- prom_printf("Invalid build_irq %d %d %016lx %016lx\n",
- pil, inofixup, iclr, imap);
- prom_halt();
- }
-
- ino = (upa_readl(imap) & (IMAP_IGN | IMAP_INO)) + inofixup;
- if (ino > NUM_IVECS) {
- prom_printf("Invalid INO %04x (%d:%d:%016lx:%016lx)\n",
- ino, pil, inofixup, iclr, imap);
- prom_halt();
- }
+ while (!cpu_online(irq_rover)) {
+ if (++irq_rover >= NR_CPUS)
+ irq_rover = 0;
+ }
+ cpuid = irq_rover;
+ do {
+ if (++irq_rover >= NR_CPUS)
+ irq_rover = 0;
+ } while (!cpu_online(irq_rover));
- bucket = &ivector_table[ino];
- if (bucket->flags & IBF_ACTIVE)
- build_irq_error("IRQ: Trying to build active INO bucket.\n",
- ino, pil, inofixup, iclr, imap, bucket);
+ spin_unlock_irqrestore(&irq_rover_lock, flags);
+ } else {
+ cpumask_t tmp;
- if (bucket->irq_info) {
- if (bucket->imap != imap || bucket->iclr != iclr)
- build_irq_error("IRQ: Trying to reinit INO bucket.\n",
- ino, pil, inofixup, iclr, imap, bucket);
+ cpus_and(tmp, cpu_online_map, mask);
- goto out;
- }
+ if (cpus_empty(tmp))
+ goto do_round_robin;
- bucket->irq_info = kzalloc(sizeof(struct irq_desc), GFP_ATOMIC);
- if (!bucket->irq_info) {
- prom_printf("IRQ: Error, kmalloc(irq_desc) failed.\n");
- prom_halt();
+ cpuid = first_cpu(tmp);
}
- /* Ok, looks good, set it up. Don't touch the irq_chain or
- * the pending flag.
- */
- bucket->imap = imap;
- bucket->iclr = iclr;
- bucket->pil = pil;
- bucket->flags = 0;
-
-out:
- return __irq(bucket);
+ return cpuid;
}
-
-unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino, int pil, unsigned char flags)
+#else
+static int irq_choose_cpu(unsigned int virt_irq)
{
- struct ino_bucket *bucket;
- unsigned long sysino;
+ return real_hard_smp_processor_id();
+}
+#endif
- sysino = sun4v_devino_to_sysino(devhandle, devino);
+static void sun4u_irq_enable(unsigned int virt_irq)
+{
+ irq_desc_t *desc = irq_desc + virt_irq;
+ struct irq_handler_data *data = desc->handler_data;
- bucket = &ivector_table[sysino];
+ if (likely(data)) {
+ unsigned long cpuid, imap;
+ unsigned int tid;
- /* Catch accidental accesses to these things. IMAP/ICLR handling
- * is done by hypervisor calls on sun4v platforms, not by direct
- * register accesses.
- *
- * But we need to make them look unique for the disable_irq() logic
- * in free_irq().
- */
- bucket->imap = ~0UL - sysino;
- bucket->iclr = ~0UL - sysino;
+ cpuid = irq_choose_cpu(virt_irq);
+ imap = data->imap;
- bucket->pil = pil;
- bucket->flags = flags;
+ tid = sun4u_compute_tid(imap, cpuid);
- bucket->irq_info = kzalloc(sizeof(struct irq_desc), GFP_ATOMIC);
- if (!bucket->irq_info) {
- prom_printf("IRQ: Error, kmalloc(irq_desc) failed.\n");
- prom_halt();
+ upa_writel(tid | IMAP_VALID, imap);
}
-
- return __irq(bucket);
}
-static void atomic_bucket_insert(struct ino_bucket *bucket)
+static void sun4u_irq_disable(unsigned int virt_irq)
{
- unsigned long pstate;
- unsigned int *ent;
+ irq_desc_t *desc = irq_desc + virt_irq;
+ struct irq_handler_data *data = desc->handler_data;
- __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
- __asm__ __volatile__("wrpr %0, %1, %%pstate"
- : : "r" (pstate), "i" (PSTATE_IE));
- ent = irq_work(smp_processor_id(), bucket->pil);
- bucket->irq_chain = *ent;
- *ent = __irq(bucket);
- __asm__ __volatile__("wrpr %0, 0x0, %%pstate" : : "r" (pstate));
-}
+ if (likely(data)) {
+ unsigned long imap = data->imap;
+ u32 tmp = upa_readl(imap);
-static int check_irq_sharing(int pil, unsigned long irqflags)
-{
- struct irqaction *action, *tmp;
-
- action = *(irq_action + pil);
- if (action) {
- if ((action->flags & SA_SHIRQ) && (irqflags & SA_SHIRQ)) {
- for (tmp = action; tmp->next; tmp = tmp->next)
- ;
- } else {
- return -EBUSY;
- }
+ tmp &= ~IMAP_VALID;
+ upa_writel(tmp, imap);
}
- return 0;
}
-static void append_irq_action(int pil, struct irqaction *action)
+static void sun4u_irq_end(unsigned int virt_irq)
{
- struct irqaction **pp = irq_action + pil;
+ irq_desc_t *desc = irq_desc + virt_irq;
+ struct irq_handler_data *data = desc->handler_data;
- while (*pp)
- pp = &((*pp)->next);
- *pp = action;
+ if (likely(data))
+ upa_writel(ICLR_IDLE, data->iclr);
}
-static struct irqaction *get_action_slot(struct ino_bucket *bucket)
+static void sun4v_irq_enable(unsigned int virt_irq)
{
- struct irq_desc *desc = bucket->irq_info;
- int max_irq, i;
+ struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
+ unsigned int ino = bucket - &ivector_table[0];
- max_irq = 1;
- if (bucket->flags & IBF_PCI)
- max_irq = MAX_IRQ_DESC_ACTION;
- for (i = 0; i < max_irq; i++) {
- struct irqaction *p = &desc->action[i];
- u32 mask = (1 << i);
+ if (likely(bucket)) {
+ unsigned long cpuid;
+ int err;
- if (desc->action_active_mask & mask)
- continue;
+ cpuid = irq_choose_cpu(virt_irq);
- desc->action_active_mask |= mask;
- return p;
+ err = sun4v_intr_settarget(ino, cpuid);
+ if (err != HV_EOK)
+ printk("sun4v_intr_settarget(%x,%lu): err(%d)\n",
+ ino, cpuid, err);
+ err = sun4v_intr_setenabled(ino, HV_INTR_ENABLED);
+ if (err != HV_EOK)
+ printk("sun4v_intr_setenabled(%x): err(%d)\n",
+ ino, err);
}
- return NULL;
}
-int request_irq(unsigned int irq, irqreturn_t (*handler)(int, void *, struct pt_regs *),
- unsigned long irqflags, const char *name, void *dev_id)
+static void sun4v_irq_disable(unsigned int virt_irq)
{
- struct irqaction *action;
- struct ino_bucket *bucket = __bucket(irq);
- unsigned long flags;
- int pending = 0;
-
- if (unlikely(!handler))
- return -EINVAL;
-
- if (unlikely(!bucket->irq_info))
- return -ENODEV;
-
- if ((bucket != &pil0_dummy_bucket) && (irqflags & SA_SAMPLE_RANDOM)) {
- /*
- * This function might sleep, we want to call it first,
- * outside of the atomic block. In SA_STATIC_ALLOC case,
- * random driver's kmalloc will fail, but it is safe.
- * If already initialized, random driver will not reinit.
- * Yes, this might clear the entropy pool if the wrong
- * driver is attempted to be loaded, without actually
- * installing a new handler, but is this really a problem,
- * only the sysadmin is able to do this.
- */
- rand_initialize_irq(irq);
- }
-
- spin_lock_irqsave(&irq_action_lock, flags);
-
- if (check_irq_sharing(bucket->pil, irqflags)) {
- spin_unlock_irqrestore(&irq_action_lock, flags);
- return -EBUSY;
- }
+ struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
+ unsigned int ino = bucket - &ivector_table[0];
- action = get_action_slot(bucket);
- if (!action) {
- spin_unlock_irqrestore(&irq_action_lock, flags);
- return -ENOMEM;
- }
+ if (likely(bucket)) {
+ int err;
- bucket->flags |= IBF_ACTIVE;
- pending = 0;
- if (bucket != &pil0_dummy_bucket) {
- pending = bucket->pending;
- if (pending)
- bucket->pending = 0;
+ err = sun4v_intr_setenabled(ino, HV_INTR_DISABLED);
+ if (err != HV_EOK)
+ printk("sun4v_intr_setenabled(%x): "
+ "err(%d)\n", ino, err);
}
+}
- action->handler = handler;
- action->flags = irqflags;
- action->name = name;
- action->next = NULL;
- action->dev_id = dev_id;
- put_ino_in_irqaction(action, irq);
- put_smpaff_in_irqaction(action, CPU_MASK_NONE);
-
- append_irq_action(bucket->pil, action);
+static void sun4v_irq_end(unsigned int virt_irq)
+{
+ struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
+ unsigned int ino = bucket - &ivector_table[0];
- enable_irq(irq);
+ if (likely(bucket)) {
+ int err;
- /* We ate the IVEC already, this makes sure it does not get lost. */
- if (pending) {
- atomic_bucket_insert(bucket);
- set_softint(1 << bucket->pil);
+ err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
+ if (err != HV_EOK)
+ printk("sun4v_intr_setstate(%x): "
+ "err(%d)\n", ino, err);
}
+}
- spin_unlock_irqrestore(&irq_action_lock, flags);
-
- if (bucket != &pil0_dummy_bucket)
- register_irq_proc(__irq_ino(irq));
+static void run_pre_handler(unsigned int virt_irq)
+{
+ struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
+ irq_desc_t *desc = irq_desc + virt_irq;
+ struct irq_handler_data *data = desc->handler_data;
-#ifdef CONFIG_SMP
- distribute_irqs();
-#endif
- return 0;
+ if (likely(data->pre_handler)) {
+ data->pre_handler(__irq_ino(__irq(bucket)),
+ data->pre_handler_arg1,
+ data->pre_handler_arg2);
+ }
}
-EXPORT_SYMBOL(request_irq);
+static struct hw_interrupt_type sun4u_irq = {
+ .typename = "sun4u",
+ .enable = sun4u_irq_enable,
+ .disable = sun4u_irq_disable,
+ .end = sun4u_irq_end,
+};
-static struct irqaction *unlink_irq_action(unsigned int irq, void *dev_id)
-{
- struct ino_bucket *bucket = __bucket(irq);
- struct irqaction *action, **pp;
+static struct hw_interrupt_type sun4u_irq_ack = {
+ .typename = "sun4u+ack",
+ .enable = sun4u_irq_enable,
+ .disable = sun4u_irq_disable,
+ .ack = run_pre_handler,
+ .end = sun4u_irq_end,
+};
- pp = irq_action + bucket->pil;
- action = *pp;
- if (unlikely(!action))
- return NULL;
+static struct hw_interrupt_type sun4v_irq = {
+ .typename = "sun4v",
+ .enable = sun4v_irq_enable,
+ .disable = sun4v_irq_disable,
+ .end = sun4v_irq_end,
+};
- if (unlikely(!action->handler)) {
- printk("Freeing free IRQ %d\n", bucket->pil);
- return NULL;
- }
+static struct hw_interrupt_type sun4v_irq_ack = {
+ .typename = "sun4v+ack",
+ .enable = sun4v_irq_enable,
+ .disable = sun4v_irq_disable,
+ .ack = run_pre_handler,
+ .end = sun4v_irq_end,
+};
- while (action && action->dev_id != dev_id) {
- pp = &action->next;
- action = *pp;
- }
+void irq_install_pre_handler(int virt_irq,
+ void (*func)(unsigned int, void *, void *),
+ void *arg1, void *arg2)
+{
+ irq_desc_t *desc = irq_desc + virt_irq;
+ struct irq_handler_data *data = desc->handler_data;
- if (likely(action))
- *pp = action->next;
+ data->pre_handler = func;
+ data->pre_handler_arg1 = arg1;
+ data->pre_handler_arg2 = arg2;
- return action;
+ desc->handler = (desc->handler == &sun4u_irq ?
+ &sun4u_irq_ack : &sun4v_irq_ack);
}
-void free_irq(unsigned int irq, void *dev_id)
+unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap)
{
- struct irqaction *action;
struct ino_bucket *bucket;
- unsigned long flags;
+ struct irq_handler_data *data;
+ irq_desc_t *desc;
+ int ino;
- spin_lock_irqsave(&irq_action_lock, flags);
+ BUG_ON(tlb_type == hypervisor);
- action = unlink_irq_action(irq, dev_id);
+ ino = (upa_readl(imap) & (IMAP_IGN | IMAP_INO)) + inofixup;
+ bucket = &ivector_table[ino];
+ if (!bucket->virt_irq) {
+ bucket->virt_irq = virt_irq_alloc(__irq(bucket));
+ irq_desc[bucket->virt_irq].handler = &sun4u_irq;
+ }
- spin_unlock_irqrestore(&irq_action_lock, flags);
+ desc = irq_desc + bucket->virt_irq;
+ if (unlikely(desc->handler_data))
+ goto out;
- if (unlikely(!action))
- return;
+ data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
+ if (unlikely(!data)) {
+ prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
+ prom_halt();
+ }
+ desc->handler_data = data;
- synchronize_irq(irq);
+ data->imap = imap;
+ data->iclr = iclr;
- spin_lock_irqsave(&irq_action_lock, flags);
+out:
+ return bucket->virt_irq;
+}
- bucket = __bucket(irq);
- if (bucket != &pil0_dummy_bucket) {
- struct irq_desc *desc = bucket->irq_info;
- int ent, i;
+unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino)
+{
+ struct ino_bucket *bucket;
+ struct irq_handler_data *data;
+ unsigned long sysino;
+ irq_desc_t *desc;
- for (i = 0; i < MAX_IRQ_DESC_ACTION; i++) {
- struct irqaction *p = &desc->action[i];
+ BUG_ON(tlb_type != hypervisor);
- if (p == action) {
- desc->action_active_mask &= ~(1 << i);
- break;
- }
- }
+ sysino = sun4v_devino_to_sysino(devhandle, devino);
+ bucket = &ivector_table[sysino];
+ if (!bucket->virt_irq) {
+ bucket->virt_irq = virt_irq_alloc(__irq(bucket));
+ irq_desc[bucket->virt_irq].handler = &sun4v_irq;
+ }
- if (!desc->action_active_mask) {
- unsigned long imap = bucket->imap;
-
- /* This unique interrupt source is now inactive. */
- bucket->flags &= ~IBF_ACTIVE;
-
- /* See if any other buckets share this bucket's IMAP
- * and are still active.
- */
- for (ent = 0; ent < NUM_IVECS; ent++) {
- struct ino_bucket *bp = &ivector_table[ent];
- if (bp != bucket &&
- bp->imap == imap &&
- (bp->flags & IBF_ACTIVE) != 0)
- break;
- }
+ desc = irq_desc + bucket->virt_irq;
+ if (unlikely(desc->handler_data))
+ goto out;
- /* Only disable when no other sub-irq levels of
- * the same IMAP are active.
- */
- if (ent == NUM_IVECS)
- disable_irq(irq);
- }
+ data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
+ if (unlikely(!data)) {
+ prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
+ prom_halt();
}
+ desc->handler_data = data;
- spin_unlock_irqrestore(&irq_action_lock, flags);
-}
+ /* Catch accidental accesses to these things. IMAP/ICLR handling
+ * is done by hypervisor calls on sun4v platforms, not by direct
+ * register accesses.
+ */
+ data->imap = ~0UL;
+ data->iclr = ~0UL;
-EXPORT_SYMBOL(free_irq);
+out:
+ return bucket->virt_irq;
+}
-#ifdef CONFIG_SMP
-void synchronize_irq(unsigned int irq)
+void hw_resend_irq(struct hw_interrupt_type *handler, unsigned int virt_irq)
{
- struct ino_bucket *bucket = __bucket(irq);
-
-#if 0
- /* The following is how I wish I could implement this.
- * Unfortunately the ICLR registers are read-only, you can
- * only write ICLR_foo values to them. To get the current
- * IRQ status you would need to get at the IRQ diag registers
- * in the PCI/SBUS controller and the layout of those vary
- * from one controller to the next, sigh... -DaveM
- */
- unsigned long iclr = bucket->iclr;
-
- while (1) {
- u32 tmp = upa_readl(iclr);
-
- if (tmp == ICLR_TRANSMIT ||
- tmp == ICLR_PENDING) {
- cpu_relax();
- continue;
- }
- break;
- }
-#else
- /* So we have to do this with a INPROGRESS bit just like x86. */
- while (bucket->flags & IBF_INPROGRESS)
- cpu_relax();
-#endif
+ struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
+ unsigned long pstate;
+ unsigned int *ent;
+
+ __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
+ __asm__ __volatile__("wrpr %0, %1, %%pstate"
+ : : "r" (pstate), "i" (PSTATE_IE));
+ ent = irq_work(smp_processor_id());
+ bucket->irq_chain = *ent;
+ *ent = __irq(bucket);
+ set_softint(1 << PIL_DEVICE_IRQ);
+ __asm__ __volatile__("wrpr %0, 0x0, %%pstate" : : "r" (pstate));
}
-#endif /* CONFIG_SMP */
-static void process_bucket(int irq, struct ino_bucket *bp, struct pt_regs *regs)
+void ack_bad_irq(unsigned int virt_irq)
{
- struct irq_desc *desc = bp->irq_info;
- unsigned char flags = bp->flags;
- u32 action_mask, i;
- int random;
+ struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
+ unsigned int ino = 0xdeadbeef;
- bp->flags |= IBF_INPROGRESS;
+ if (bucket)
+ ino = bucket - &ivector_table[0];
- if (unlikely(!(flags & IBF_ACTIVE))) {
- bp->pending = 1;
- goto out;
- }
-
- if (desc->pre_handler)
- desc->pre_handler(bp,
- desc->pre_handler_arg1,
- desc->pre_handler_arg2);
+ printk(KERN_CRIT "Unexpected IRQ from ino[%x] virt_irq[%u]\n",
+ ino, virt_irq);
+}
- action_mask = desc->action_active_mask;
- random = 0;
- for (i = 0; i < MAX_IRQ_DESC_ACTION; i++) {
- struct irqaction *p = &desc->action[i];
- u32 mask = (1 << i);
+#ifndef CONFIG_SMP
+extern irqreturn_t timer_interrupt(int, void *, struct pt_regs *);
- if (!(action_mask & mask))
- continue;
+void timer_irq(int irq, struct pt_regs *regs)
+{
+ unsigned long clr_mask = 1 << irq;
+ unsigned long tick_mask = tick_ops->softint_mask;
- action_mask &= ~mask;
+ if (get_softint() & tick_mask) {
+ irq = 0;
+ clr_mask = tick_mask;
+ }
+ clear_softint(clr_mask);
- if (p->handler(__irq(bp), p->dev_id, regs) == IRQ_HANDLED)
- random |= p->flags;
+ irq_enter();
- if (!action_mask)
- break;
- }
- if (bp->pil != 0) {
- if (tlb_type == hypervisor) {
- unsigned int ino = __irq_ino(bp);
- int err;
-
- err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
- if (err != HV_EOK)
- printk("sun4v_intr_setstate(%x): "
- "err(%d)\n", ino, err);
- } else {
- upa_writel(ICLR_IDLE, bp->iclr);
- }
+ kstat_this_cpu.irqs[0]++;
+ timer_interrupt(irq, NULL, regs);
- /* Test and add entropy */
- if (random & SA_SAMPLE_RANDOM)
- add_interrupt_randomness(irq);
- }
-out:
- bp->flags &= ~IBF_INPROGRESS;
+ irq_exit();
}
+#endif
void handler_irq(int irq, struct pt_regs *regs)
{
- struct ino_bucket *bp;
- int cpu = smp_processor_id();
-
-#ifndef CONFIG_SMP
- /*
- * Check for TICK_INT on level 14 softint.
- */
- {
- unsigned long clr_mask = 1 << irq;
- unsigned long tick_mask = tick_ops->softint_mask;
+ struct ino_bucket *bucket;
- if ((irq == 14) && (get_softint() & tick_mask)) {
- irq = 0;
- clr_mask = tick_mask;
- }
- clear_softint(clr_mask);
- }
-#else
clear_softint(1 << irq);
-#endif
irq_enter();
- kstat_this_cpu.irqs[irq]++;
/* Sliiiick... */
-#ifndef CONFIG_SMP
- bp = ((irq != 0) ?
- __bucket(xchg32(irq_work(cpu, irq), 0)) :
- &pil0_dummy_bucket);
-#else
- bp = __bucket(xchg32(irq_work(cpu, irq), 0));
-#endif
- while (bp) {
- struct ino_bucket *nbp = __bucket(bp->irq_chain);
+ bucket = __bucket(xchg32(irq_work(smp_processor_id()), 0));
+ while (bucket) {
+ struct ino_bucket *next = __bucket(bucket->irq_chain);
- bp->irq_chain = 0;
- process_bucket(irq, bp, regs);
- bp = nbp;
+ bucket->irq_chain = 0;
+ __do_IRQ(bucket->virt_irq, regs);
+
+ bucket = next;
}
+
irq_exit();
}
@@ -787,81 +623,6 @@ main_interrupt:
EXPORT_SYMBOL(sparc_floppy_irq);
#endif
-/* We really don't need these at all on the Sparc. We only have
- * stubs here because they are exported to modules.
- */
-unsigned long probe_irq_on(void)
-{
- return 0;
-}
-
-EXPORT_SYMBOL(probe_irq_on);
-
-int probe_irq_off(unsigned long mask)
-{
- return 0;
-}
-
-EXPORT_SYMBOL(probe_irq_off);
-
-#ifdef CONFIG_SMP
-static int retarget_one_irq(struct irqaction *p, int goal_cpu)
-{
- struct ino_bucket *bucket = get_ino_in_irqaction(p) + ivector_table;
-
- while (!cpu_online(goal_cpu)) {
- if (++goal_cpu >= NR_CPUS)
- goal_cpu = 0;
- }
-
- if (tlb_type == hypervisor) {
- unsigned int ino = __irq_ino(bucket);
-
- sun4v_intr_settarget(ino, goal_cpu);
- sun4v_intr_setenabled(ino, HV_INTR_ENABLED);
- } else {
- unsigned long imap = bucket->imap;
- unsigned int tid = sun4u_compute_tid(imap, goal_cpu);
-
- upa_writel(tid | IMAP_VALID, imap);
- }
-
- do {
- if (++goal_cpu >= NR_CPUS)
- goal_cpu = 0;
- } while (!cpu_online(goal_cpu));
-
- return goal_cpu;
-}
-
-/* Called from request_irq. */
-static void distribute_irqs(void)
-{
- unsigned long flags;
- int cpu, level;
-
- spin_lock_irqsave(&irq_action_lock, flags);
- cpu = 0;
-
- /*
- * Skip the timer at [0], and very rare error/power intrs at [15].
- * Also level [12], it causes problems on Ex000 systems.
- */
- for (level = 1; level < NR_IRQS; level++) {
- struct irqaction *p = irq_action[level];
-
- if (level == 12)
- continue;
-
- while(p) {
- cpu = retarget_one_irq(p, cpu);
- p = p->next;
- }
- }
- spin_unlock_irqrestore(&irq_action_lock, flags);
-}
-#endif
-
struct sun5_timer {
u64 count0;
u64 limit0;
@@ -929,7 +690,7 @@ void init_irqwork_curcpu(void)
{
int cpu = hard_smp_processor_id();
- memset(__irq_work + cpu, 0, sizeof(struct irq_work_struct));
+ trap_block[cpu].irq_worklist = 0;
}
static void __cpuinit register_one_mondo(unsigned long paddr, unsigned long type)
@@ -1037,6 +798,10 @@ void __cpuinit sun4v_init_mondo_queues(int use_bootmem, int cpu, int alloc, int
}
}
+static struct irqaction timer_irq_action = {
+ .name = "timer",
+};
+
/* Only invoked on boot processor. */
void __init init_IRQ(void)
{
@@ -1064,109 +829,6 @@ void __init init_IRQ(void)
: /* No outputs */
: "i" (PSTATE_IE)
: "g1");
-}
-static struct proc_dir_entry * root_irq_dir;
-static struct proc_dir_entry * irq_dir [NUM_IVECS];
-
-#ifdef CONFIG_SMP
-
-static int irq_affinity_read_proc (char *page, char **start, off_t off,
- int count, int *eof, void *data)
-{
- struct ino_bucket *bp = ivector_table + (long)data;
- struct irq_desc *desc = bp->irq_info;
- struct irqaction *ap = desc->action;
- cpumask_t mask;
- int len;
-
- mask = get_smpaff_in_irqaction(ap);
- if (cpus_empty(mask))
- mask = cpu_online_map;
-
- len = cpumask_scnprintf(page, count, mask);
- if (count - len < 2)
- return -EINVAL;
- len += sprintf(page + len, "\n");
- return len;
-}
-
-static inline void set_intr_affinity(int irq, cpumask_t hw_aff)
-{
- struct ino_bucket *bp = ivector_table + irq;
- struct irq_desc *desc = bp->irq_info;
- struct irqaction *ap = desc->action;
-
- /* Users specify affinity in terms of hw cpu ids.
- * As soon as we do this, handler_irq() might see and take action.
- */
- put_smpaff_in_irqaction(ap, hw_aff);
-
- /* Migration is simply done by the next cpu to service this
- * interrupt.
- */
-}
-
-static int irq_affinity_write_proc (struct file *file, const char __user *buffer,
- unsigned long count, void *data)
-{
- int irq = (long) data, full_count = count, err;
- cpumask_t new_value;
-
- err = cpumask_parse(buffer, count, new_value);
-
- /*
- * Do not allow disabling IRQs completely - it's a too easy
- * way to make the system unusable accidentally :-) At least
- * one online CPU still has to be targeted.
- */
- cpus_and(new_value, new_value, cpu_online_map);
- if (cpus_empty(new_value))
- return -EINVAL;
-
- set_intr_affinity(irq, new_value);
-
- return full_count;
+ irq_desc[0].action = &timer_irq_action;
}
-
-#endif
-
-#define MAX_NAMELEN 10
-
-static void register_irq_proc (unsigned int irq)
-{
- char name [MAX_NAMELEN];
-
- if (!root_irq_dir || irq_dir[irq])
- return;
-
- memset(name, 0, MAX_NAMELEN);
- sprintf(name, "%x", irq);
-
- /* create /proc/irq/1234 */
- irq_dir[irq] = proc_mkdir(name, root_irq_dir);
-
-#ifdef CONFIG_SMP
- /* XXX SMP affinity not supported on starfire yet. */
- if (this_is_starfire == 0) {
- struct proc_dir_entry *entry;
-
- /* create /proc/irq/1234/smp_affinity */
- entry = create_proc_entry("smp_affinity", 0600, irq_dir[irq]);
-
- if (entry) {
- entry->nlink = 1;
- entry->data = (void *)(long)irq;
- entry->read_proc = irq_affinity_read_proc;
- entry->write_proc = irq_affinity_write_proc;
- }
- }
-#endif
-}
-
-void init_irq_proc (void)
-{
- /* create /proc/irq */
- root_irq_dir = proc_mkdir("irq", NULL);
-}
-
diff --git a/arch/sparc64/kernel/pci.c b/arch/sparc64/kernel/pci.c
index f97ddeb105a..9472580a431 100644
--- a/arch/sparc64/kernel/pci.c
+++ b/arch/sparc64/kernel/pci.c
@@ -47,12 +47,6 @@ struct pci_controller_info *pci_controller_root = NULL;
/* Each PCI controller found gets a unique index. */
int pci_num_controllers = 0;
-/* At boot time the user can give the kernel a command
- * line option which controls if and how PCI devices
- * are reordered at PCI bus probing time.
- */
-int pci_device_reorder = 0;
-
volatile int pci_poke_in_progress;
volatile int pci_poke_cpu = -1;
volatile int pci_poke_faulted;
@@ -316,27 +310,6 @@ static void __init pci_scan_each_controller_bus(void)
p->scan_bus(p);
}
-/* Reorder the pci_dev chain, so that onboard devices come first
- * and then come the pluggable cards.
- */
-static void __init pci_reorder_devs(void)
-{
- struct list_head *pci_onboard = &pci_devices;
- struct list_head *walk = pci_onboard->next;
-
- while (walk != pci_onboard) {
- struct pci_dev *pdev = pci_dev_g(walk);
- struct list_head *walk_next = walk->next;
-
- if (pdev->irq && (__irq_ino(pdev->irq) & 0x20)) {
- list_del(walk);
- list_add(walk, pci_onboard);
- }
-
- walk = walk_next;
- }
-}
-
extern void clock_probe(void);
extern void power_init(void);
@@ -348,9 +321,6 @@ static int __init pcibios_init(void)
pci_scan_each_controller_bus();
- if (pci_device_reorder)
- pci_reorder_devs();
-
isa_init();
ebus_init();
clock_probe();
@@ -441,14 +411,6 @@ EXPORT_SYMBOL(pcibios_bus_to_resource);
char * __init pcibios_setup(char *str)
{
- if (!strcmp(str, "onboardfirst")) {
- pci_device_reorder = 1;
- return NULL;
- }
- if (!strcmp(str, "noreorder")) {
- pci_device_reorder = 0;
- return NULL;
- }
return str;
}
diff --git a/arch/sparc64/kernel/pci_psycho.c b/arch/sparc64/kernel/pci_psycho.c
index d17878b145c..24db22aa972 100644
--- a/arch/sparc64/kernel/pci_psycho.c
+++ b/arch/sparc64/kernel/pci_psycho.c
@@ -276,82 +276,13 @@ static unsigned long __onboard_imap_off[] = {
((ino & 0x20) ? (PSYCHO_ICLR_SCSI + (((ino) & 0x1f) << 3)) : \
(PSYCHO_ICLR_A_SLOT0 + (((ino) & 0x1f)<<3)))
-/* PCI PSYCHO INO number to Sparc PIL level. */
-static unsigned char psycho_pil_table[] = {
-/*0x00*/0, 0, 0, 0, /* PCI A slot 0 Int A, B, C, D */
-/*0x04*/0, 0, 0, 0, /* PCI A slot 1 Int A, B, C, D */
-/*0x08*/0, 0, 0, 0, /* PCI A slot 2 Int A, B, C, D */
-/*0x0c*/0, 0, 0, 0, /* PCI A slot 3 Int A, B, C, D */
-/*0x10*/0, 0, 0, 0, /* PCI B slot 0 Int A, B, C, D */
-/*0x14*/0, 0, 0, 0, /* PCI B slot 1 Int A, B, C, D */
-/*0x18*/0, 0, 0, 0, /* PCI B slot 2 Int A, B, C, D */
-/*0x1c*/0, 0, 0, 0, /* PCI B slot 3 Int A, B, C, D */
-/*0x20*/5, /* SCSI */
-/*0x21*/5, /* Ethernet */
-/*0x22*/8, /* Parallel Port */
-/*0x23*/13, /* Audio Record */
-/*0x24*/14, /* Audio Playback */
-/*0x25*/15, /* PowerFail */
-/*0x26*/5, /* second SCSI */
-/*0x27*/11, /* Floppy */
-/*0x28*/5, /* Spare Hardware */
-/*0x29*/9, /* Keyboard */
-/*0x2a*/5, /* Mouse */
-/*0x2b*/12, /* Serial */
-/*0x2c*/10, /* Timer 0 */
-/*0x2d*/11, /* Timer 1 */
-/*0x2e*/15, /* Uncorrectable ECC */
-/*0x2f*/15, /* Correctable ECC */
-/*0x30*/15, /* PCI Bus A Error */
-/*0x31*/15, /* PCI Bus B Error */
-/*0x32*/15, /* Power Management */
-};
-
-static int psycho_ino_to_pil(struct pci_dev *pdev, unsigned int ino)
-{
- int ret;
-
- ret = psycho_pil_table[ino];
- if (ret == 0 && pdev == NULL) {
- ret = 5;
- } else if (ret == 0) {
- switch ((pdev->class >> 16) & 0xff) {
- case PCI_BASE_CLASS_STORAGE:
- ret = 5;
- break;
-
- case PCI_BASE_CLASS_NETWORK:
- ret = 6;
- break;
-
- case PCI_BASE_CLASS_DISPLAY:
- ret = 9;
- break;
-
- case PCI_BASE_CLASS_MULTIMEDIA:
- case PCI_BASE_CLASS_MEMORY:
- case PCI_BASE_CLASS_BRIDGE:
- case PCI_BASE_CLASS_SERIAL:
- ret = 10;
- break;
-
- default:
- ret = 5;
- break;
- };
- }
-
- return ret;
-}
-
static unsigned int psycho_irq_build(struct pci_pbm_info *pbm,
struct pci_dev *pdev,
unsigned int ino)
{
- struct ino_bucket *bucket;
unsigned long imap, iclr;
unsigned long imap_off, iclr_off;
- int pil, inofixup = 0;
+ int inofixup = 0;
ino &= PCI_IRQ_INO;
if (ino < PSYCHO_ONBOARD_IRQ_BASE) {
@@ -367,11 +298,6 @@ static unsigned int psycho_irq_build(struct pci_pbm_info *pbm,
}
/* Now build the IRQ bucket. */
- pil = psycho_ino_to_pil(pdev, ino);
-
- if (PIL_RESERVED(pil))
- BUG();
-
imap = pbm->controller_regs + imap_off;
imap += 4;
@@ -382,10 +308,7 @@ static unsigned int psycho_irq_build(struct pci_pbm_info *pbm,
if ((ino & 0x20) == 0)
inofixup = ino & 0x03;
- bucket = __bucket(build_irq(pil, inofixup, iclr, imap));
- bucket->flags |= IBF_PCI;
-
- return __irq(bucket);
+ return build_irq(inofixup, iclr, imap);
}
/* PSYCHO error handling support. */
diff --git a/arch/sparc64/kernel/pci_sabre.c b/arch/sparc64/kernel/pci_sabre.c
index f67bb7f078c..b7d997b55f0 100644
--- a/arch/sparc64/kernel/pci_sabre.c
+++ b/arch/sparc64/kernel/pci_sabre.c
@@ -523,78 +523,6 @@ static unsigned long __onboard_imap_off[] = {
((ino & 0x20) ? (SABRE_ICLR_SCSI + (((ino) & 0x1f) << 3)) : \
(SABRE_ICLR_A_SLOT0 + (((ino) & 0x1f)<<3)))
-/* PCI SABRE INO number to Sparc PIL level. */
-static unsigned char sabre_pil_table[] = {
-/*0x00*/0, 0, 0, 0, /* PCI A slot 0 Int A, B, C, D */
-/*0x04*/0, 0, 0, 0, /* PCI A slot 1 Int A, B, C, D */
-/*0x08*/0, 0, 0, 0, /* PCI A slot 2 Int A, B, C, D */
-/*0x0c*/0, 0, 0, 0, /* PCI A slot 3 Int A, B, C, D */
-/*0x10*/0, 0, 0, 0, /* PCI B slot 0 Int A, B, C, D */
-/*0x14*/0, 0, 0, 0, /* PCI B slot 1 Int A, B, C, D */
-/*0x18*/0, 0, 0, 0, /* PCI B slot 2 Int A, B, C, D */
-/*0x1c*/0, 0, 0, 0, /* PCI B slot 3 Int A, B, C, D */
-/*0x20*/5, /* SCSI */
-/*0x21*/5, /* Ethernet */
-/*0x22*/8, /* Parallel Port */
-/*0x23*/13, /* Audio Record */
-/*0x24*/14, /* Audio Playback */
-/*0x25*/15, /* PowerFail */
-/*0x26*/5, /* second SCSI */
-/*0x27*/11, /* Floppy */
-/*0x28*/5, /* Spare Hardware */
-/*0x29*/9, /* Keyboard */
-/*0x2a*/5, /* Mouse */
-/*0x2b*/12, /* Serial */
-/*0x2c*/10, /* Timer 0 */
-/*0x2d*/11, /* Timer 1 */
-/*0x2e*/15, /* Uncorrectable ECC */
-/*0x2f*/15, /* Correctable ECC */
-/*0x30*/15, /* PCI Bus A Error */
-/*0x31*/15, /* PCI Bus B Error */
-/*0x32*/15, /* Power Management */
-};
-
-static int sabre_ino_to_pil(struct pci_dev *pdev, unsigned int ino)
-{
- int ret;
-
- if (pdev &&
- pdev->vendor == PCI_VENDOR_ID_SUN &&
- pdev->device == PCI_DEVICE_ID_SUN_RIO_USB)
- return 9;
-
- ret = sabre_pil_table[ino];
- if (ret == 0 && pdev == NULL) {
- ret = 5;
- } else if (ret == 0) {
- switch ((pdev->class >> 16) & 0xff) {
- case PCI_BASE_CLASS_STORAGE:
- ret = 5;
- break;
-
- case PCI_BASE_CLASS_NETWORK:
- ret = 6;
- break;
-
- case PCI_BASE_CLASS_DISPLAY:
- ret = 9;
- break;
-
- case PCI_BASE_CLASS_MULTIMEDIA:
- case PCI_BASE_CLASS_MEMORY:
- case PCI_BASE_CLASS_BRIDGE:
- case PCI_BASE_CLASS_SERIAL:
- ret = 10;
- break;
-
- default:
- ret = 5;
- break;
- };
- }
- return ret;
-}
-
/* When a device lives behind a bridge deeper in the PCI bus topology
* than APB, a special sequence must run to make sure all pending DMA
* transfers at the time of IRQ delivery are visible in the coherency
@@ -602,7 +530,7 @@ static int sabre_ino_to_pil(struct pci_dev *pdev, unsigned int ino)
* side of the non-APB bridge, then perform a read of Sabre's DMA
* write-sync register.
*/
-static void sabre_wsync_handler(struct ino_bucket *bucket, void *_arg1, void *_arg2)
+static void sabre_wsync_handler(unsigned int ino, void *_arg1, void *_arg2)
{
struct pci_dev *pdev = _arg1;
unsigned long sync_reg = (unsigned long) _arg2;
@@ -616,10 +544,10 @@ static unsigned int sabre_irq_build(struct pci_pbm_info *pbm,
struct pci_dev *pdev,
unsigned int ino)
{
- struct ino_bucket *bucket;
unsigned long imap, iclr;
unsigned long imap_off, iclr_off;
- int pil, inofixup = 0;
+ int inofixup = 0;
+ int virt_irq;
ino &= PCI_IRQ_INO;
if (ino < SABRE_ONBOARD_IRQ_BASE) {
@@ -635,11 +563,6 @@ static unsigned int sabre_irq_build(struct pci_pbm_info *pbm,
}
/* Now build the IRQ bucket. */
- pil = sabre_ino_to_pil(pdev, ino);
-
- if (PIL_RESERVED(pil))
- BUG();
-
imap = pbm->controller_regs + imap_off;
imap += 4;
@@ -650,23 +573,23 @@ static unsigned int sabre_irq_build(struct pci_pbm_info *pbm,
if ((ino & 0x20) == 0)
inofixup = ino & 0x03;
- bucket = __bucket(build_irq(pil, inofixup, iclr, imap));
- bucket->flags |= IBF_PCI;
+ virt_irq = build_irq(inofixup, iclr, imap);
if (pdev) {
struct pcidev_cookie *pcp = pdev->sysdata;
if (pdev->bus->number != pcp->pbm->pci_first_busno) {
struct pci_controller_info *p = pcp->pbm->parent;
- struct irq_desc *d = bucket->irq_info;
- d->pre_handler = sabre_wsync_handler;
- d->pre_handler_arg1 = pdev;
- d->pre_handler_arg2 = (void *)
- p->pbm_A.controller_regs + SABRE_WRSYNC;
+ irq_install_pre_handler(virt_irq,
+ sabre_wsync_handler,
+ pdev,
+ (void *)
+ p->pbm_A.controller_regs +
+ SABRE_WRSYNC);
}
}
- return __irq(bucket);
+ return virt_irq;
}
/* SABRE error handling support. */
diff --git a/arch/sparc64/kernel/pci_schizo.c b/arch/sparc64/kernel/pci_schizo.c
index 7fe4de03ac2..cc662e915d3 100644
--- a/arch/sparc64/kernel/pci_schizo.c
+++ b/arch/sparc64/kernel/pci_schizo.c
@@ -232,105 +232,10 @@ static unsigned long schizo_iclr_offset(unsigned long ino)
return SCHIZO_ICLR_BASE + (ino * 8UL);
}
-/* PCI SCHIZO INO number to Sparc PIL level. This table only matters for
- * INOs which will not have an associated PCI device struct, ie. onboard
- * EBUS devices and PCI controller internal error interrupts.
- */
-static unsigned char schizo_pil_table[] = {
-/*0x00*/0, 0, 0, 0, /* PCI slot 0 Int A, B, C, D */
-/*0x04*/0, 0, 0, 0, /* PCI slot 1 Int A, B, C, D */
-/*0x08*/0, 0, 0, 0, /* PCI slot 2 Int A, B, C, D */
-/*0x0c*/0, 0, 0, 0, /* PCI slot 3 Int A, B, C, D */
-/*0x10*/0, 0, 0, 0, /* PCI slot 4 Int A, B, C, D */
-/*0x14*/0, 0, 0, 0, /* PCI slot 5 Int A, B, C, D */
-/*0x18*/5, /* SCSI */
-/*0x19*/5, /* second SCSI */
-/*0x1a*/0, /* UNKNOWN */
-/*0x1b*/0, /* UNKNOWN */
-/*0x1c*/8, /* Parallel */
-/*0x1d*/5, /* Ethernet */
-/*0x1e*/8, /* Firewire-1394 */
-/*0x1f*/9, /* USB */
-/*0x20*/13, /* Audio Record */
-/*0x21*/14, /* Audio Playback */
-/*0x22*/12, /* Serial */
-/*0x23*/5, /* EBUS I2C */
-/*0x24*/10, /* RTC Clock */
-/*0x25*/11, /* Floppy */
-/*0x26*/0, /* UNKNOWN */
-/*0x27*/0, /* UNKNOWN */
-/*0x28*/0, /* UNKNOWN */
-/*0x29*/0, /* UNKNOWN */
-/*0x2a*/10, /* UPA 1 */
-/*0x2b*/10, /* UPA 2 */
-/*0x2c*/0, /* UNKNOWN */
-/*0x2d*/0, /* UNKNOWN */
-/*0x2e*/0, /* UNKNOWN */
-/*0x2f*/0, /* UNKNOWN */
-/*0x30*/15, /* Uncorrectable ECC */
-/*0x31*/15, /* Correctable ECC */
-/*0x32*/15, /* PCI Bus A Error */
-/*0x33*/15, /* PCI Bus B Error */
-/*0x34*/15, /* Safari Bus Error */
-/*0x35*/0, /* Reserved */
-/*0x36*/0, /* Reserved */
-/*0x37*/0, /* Reserved */
-/*0x38*/0, /* Reserved for NewLink */
-/*0x39*/0, /* Reserved for NewLink */
-/*0x3a*/0, /* Reserved for NewLink */
-/*0x3b*/0, /* Reserved for NewLink */
-/*0x3c*/0, /* Reserved for NewLink */
-/*0x3d*/0, /* Reserved for NewLink */
-/*0x3e*/0, /* Reserved for NewLink */
-/*0x3f*/0, /* Reserved for NewLink */
-};
-
-static int schizo_ino_to_pil(struct pci_dev *pdev, unsigned int ino)
-{
- int ret;
-
- if (pdev &&
- pdev->vendor == PCI_VENDOR_ID_SUN &&
- pdev->device == PCI_DEVICE_ID_SUN_RIO_USB)
- return 9;
-
- ret = schizo_pil_table[ino];
- if (ret == 0 && pdev == NULL) {
- ret = 5;
- } else if (ret == 0) {
- switch ((pdev->class >> 16) & 0xff) {
- case PCI_BASE_CLASS_STORAGE:
- ret = 5;
- break;
-
- case PCI_BASE_CLASS_NETWORK:
- ret = 6;
- break;
-
- case PCI_BASE_CLASS_DISPLAY:
- ret = 9;
- break;
-
- case PCI_BASE_CLASS_MULTIMEDIA:
- case PCI_BASE_CLASS_MEMORY:
- case PCI_BASE_CLASS_BRIDGE:
- case PCI_BASE_CLASS_SERIAL:
- ret = 10;
- break;
-
- default:
- ret = 5;
- break;
- };
- }
-
- return ret;
-}
-
-static void tomatillo_wsync_handler(struct ino_bucket *bucket, void *_arg1, void *_arg2)
+static void tomatillo_wsync_handler(unsigned int ino, void *_arg1, void *_arg2)
{
unsigned long sync_reg = (unsigned long) _arg2;
- u64 mask = 1UL << (__irq_ino(__irq(bucket)) & IMAP_INO);
+ u64 mask = 1UL << (ino & IMAP_INO);
u64 val;
int limit;
@@ -365,30 +270,33 @@ static void tomatillo_wsync_handler(struct ino_bucket *bucket, void *_arg1, void
}
}
+static unsigned long schizo_ino_to_iclr(struct pci_pbm_info *pbm,
+ unsigned int ino)
+{
+ ino &= PCI_IRQ_INO;
+ return pbm->pbm_regs + schizo_iclr_offset(ino) + 4;
+}
+
+static unsigned long schizo_ino_to_imap(struct pci_pbm_info *pbm,
+ unsigned int ino)
+{
+ ino &= PCI_IRQ_INO;
+ return pbm->pbm_regs + schizo_imap_offset(ino) + 4;
+}
+
static unsigned int schizo_irq_build(struct pci_pbm_info *pbm,
struct pci_dev *pdev,
unsigned int ino)
{
- struct ino_bucket *bucket;
unsigned long imap, iclr;
- unsigned long imap_off, iclr_off;
- int pil, ign_fixup;
+ int ign_fixup;
+ int virt_irq;
ino &= PCI_IRQ_INO;
- imap_off = schizo_imap_offset(ino);
/* Now build the IRQ bucket. */
- pil = schizo_ino_to_pil(pdev, ino);
-
- if (PIL_RESERVED(pil))
- BUG();
-
- imap = pbm->pbm_regs + imap_off;
- imap += 4;
-
- iclr_off = schizo_iclr_offset(ino);
- iclr = pbm->pbm_regs + iclr_off;
- iclr += 4;
+ imap = schizo_ino_to_imap(pbm, ino);
+ iclr = schizo_ino_to_iclr(pbm, ino);
/* On Schizo, no inofixup occurs. This is because each
* INO has it's own IMAP register. On Psycho and Sabre
@@ -405,19 +313,17 @@ static unsigned int schizo_irq_build(struct pci_pbm_info *pbm,
ign_fixup = (1 << 6);
}
- bucket = __bucket(build_irq(pil, ign_fixup, iclr, imap));
- bucket->flags |= IBF_PCI;
+ virt_irq = build_irq(ign_fixup, iclr, imap);
if (pdev && pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) {
- struct irq_desc *p = bucket->irq_info;
-
- p->pre_handler = tomatillo_wsync_handler;
- p->pre_handler_arg1 = ((pbm->chip_version <= 4) ?
- (void *) 1 : (void *) 0);
- p->pre_handler_arg2 = (void *) pbm->sync_reg;
+ irq_install_pre_handler(virt_irq,
+ tomatillo_wsync_handler,
+ ((pbm->chip_version <= 4) ?
+ (void *) 1 : (void *) 0),
+ (void *) pbm->sync_reg);
}
- return __irq(bucket);
+ return virt_irq;
}
/* SCHIZO error handling support. */
@@ -458,7 +364,6 @@ struct pci_pbm_info *pbm_for_ino(struct pci_controller_info *p, u32 ino)
static void schizo_clear_other_err_intr(struct pci_controller_info *p, int irq)
{
struct pci_pbm_info *pbm;
- struct ino_bucket *bucket;
unsigned long iclr;
/* Do not clear the interrupt for the other PCI bus.
@@ -476,11 +381,11 @@ static void schizo_clear_other_err_intr(struct pci_controller_info *p, int irq)
else
pbm = &p->pbm_A;
- irq = schizo_irq_build(pbm, NULL,
- (pbm->portid << 6) | (irq & IMAP_INO));
- bucket = __bucket(irq);
- iclr = bucket->iclr;
+ schizo_irq_build(pbm, NULL,
+ (pbm->portid << 6) | (irq & IMAP_INO));
+ iclr = schizo_ino_to_iclr(pbm,
+ (pbm->portid << 6) | (irq & IMAP_INO));
upa_writel(ICLR_IDLE, iclr);
}
@@ -1225,7 +1130,6 @@ static void tomatillo_register_error_handlers(struct pci_controller_info *p)
{
struct pci_pbm_info *pbm;
unsigned int irq;
- struct ino_bucket *bucket;
u64 tmp, err_mask, err_no_mask;
/* Build IRQs and register handlers. */
@@ -1237,8 +1141,7 @@ static void tomatillo_register_error_handlers(struct pci_controller_info *p)
pbm->name);
prom_halt();
}
- bucket = __bucket(irq);
- tmp = upa_readl(bucket->imap);
+ tmp = upa_readl(schizo_ino_to_imap(pbm, (pbm->portid << 6) | SCHIZO_UE_INO));
upa_writel(tmp, (pbm->pbm_regs +
schizo_imap_offset(SCHIZO_UE_INO) + 4));
@@ -1250,8 +1153,7 @@ static void tomatillo_register_error_handlers(struct pci_controller_info *p)
pbm->name);
prom_halt();
}
- bucket = __bucket(irq);
- tmp = upa_readl(bucket->imap);
+ tmp = upa_readl(schizo_ino_to_imap(pbm, (pbm->portid << 6) | SCHIZO_CE_INO));
upa_writel(tmp, (pbm->pbm_regs +
schizo_imap_offset(SCHIZO_CE_INO) + 4));
@@ -1264,8 +1166,8 @@ static void tomatillo_register_error_handlers(struct pci_controller_info *p)
pbm->name);
prom_halt();
}
- bucket = __bucket(irq);
- tmp = upa_readl(bucket->imap);
+ tmp = upa_readl(schizo_ino_to_imap(pbm, ((pbm->portid << 6) |
+ SCHIZO_PCIERR_A_INO)));
upa_writel(tmp, (pbm->pbm_regs +
schizo_imap_offset(SCHIZO_PCIERR_A_INO) + 4));
@@ -1278,8 +1180,8 @@ static void tomatillo_register_error_handlers(struct pci_controller_info *p)
pbm->name);
prom_halt();
}
- bucket = __bucket(irq);
- tmp = upa_readl(bucket->imap);
+ tmp = upa_readl(schizo_ino_to_imap(pbm, ((pbm->portid << 6) |
+ SCHIZO_PCIERR_B_INO)));
upa_writel(tmp, (pbm->pbm_regs +
schizo_imap_offset(SCHIZO_PCIERR_B_INO) + 4));
@@ -1291,8 +1193,8 @@ static void tomatillo_register_error_handlers(struct pci_controller_info *p)
pbm->name);
prom_halt();
}
- bucket = __bucket(irq);
- tmp = upa_readl(bucket->imap);
+ tmp = upa_readl(schizo_ino_to_imap(pbm, ((pbm->portid << 6) |
+ SCHIZO_SERR_INO)));
upa_writel(tmp, (pbm->pbm_regs +
schizo_imap_offset(SCHIZO_SERR_INO) + 4));
@@ -1363,7 +1265,6 @@ static void schizo_register_error_handlers(struct pci_controller_info *p)
{
struct pci_pbm_info *pbm;
unsigned int irq;
- struct ino_bucket *bucket;
u64 tmp, err_mask, err_no_mask;
/* Build IRQs and register handlers. */
@@ -1375,8 +1276,7 @@ static void schizo_register_error_handlers(struct pci_controller_info *p)
pbm->name);
prom_halt();
}
- bucket = __bucket(irq);
- tmp = upa_readl(bucket->imap);
+ tmp = upa_readl(schizo_ino_to_imap(pbm, (pbm->portid << 6) | SCHIZO_UE_INO));
upa_writel(tmp, (pbm->pbm_regs + schizo_imap_offset(SCHIZO_UE_INO) + 4));
pbm = pbm_for_ino(p, SCHIZO_CE_INO);
@@ -1387,8 +1287,7 @@ static void schizo_register_error_handlers(struct pci_controller_info *p)
pbm->name);
prom_halt();
}
- bucket = __bucket(irq);
- tmp = upa_readl(bucket->imap);
+ tmp = upa_readl(schizo_ino_to_imap(pbm, (pbm->portid << 6) | SCHIZO_CE_INO));
upa_writel(tmp, (pbm->pbm_regs + schizo_imap_offset(SCHIZO_CE_INO) + 4));
pbm = pbm_for_ino(p, SCHIZO_PCIERR_A_INO);
@@ -1399,8 +1298,7 @@ static void schizo_register_error_handlers(struct pci_controller_info *p)
pbm->name);
prom_halt();
}
- bucket = __bucket(irq);
- tmp = upa_readl(bucket->imap);
+ tmp = upa_readl(schizo_ino_to_imap(pbm, (pbm->portid << 6) | SCHIZO_PCIERR_A_INO));
upa_writel(tmp, (pbm->pbm_regs + schizo_imap_offset(SCHIZO_PCIERR_A_INO) + 4));
pbm = pbm_for_ino(p, SCHIZO_PCIERR_B_INO);
@@ -1411,8 +1309,7 @@ static void schizo_register_error_handlers(struct pci_controller_info *p)
pbm->name);
prom_halt();
}
- bucket = __bucket(irq);
- tmp = upa_readl(bucket->imap);
+ tmp = upa_readl(schizo_ino_to_imap(pbm, (pbm->portid << 6) | SCHIZO_PCIERR_B_INO));
upa_writel(tmp, (pbm->pbm_regs + schizo_imap_offset(SCHIZO_PCIERR_B_INO) + 4));
pbm = pbm_for_ino(p, SCHIZO_SERR_INO);
@@ -1423,8 +1320,7 @@ static void schizo_register_error_handlers(struct pci_controller_info *p)
pbm->name);
prom_halt();
}
- bucket = __bucket(irq);
- tmp = upa_readl(bucket->imap);
+ tmp = upa_readl(schizo_ino_to_imap(pbm, (pbm->portid << 6) | SCHIZO_SERR_INO));
upa_writel(tmp, (pbm->pbm_regs + schizo_imap_offset(SCHIZO_SERR_INO) + 4));
/* Enable UE and CE interrupts for controller. */
diff --git a/arch/sparc64/kernel/pci_sun4v.c b/arch/sparc64/kernel/pci_sun4v.c
index 0c089520297..5419480edf4 100644
--- a/arch/sparc64/kernel/pci_sun4v.c
+++ b/arch/sparc64/kernel/pci_sun4v.c
@@ -843,38 +843,8 @@ static unsigned int pci_sun4v_irq_build(struct pci_pbm_info *pbm,
unsigned int devino)
{
u32 devhandle = pbm->devhandle;
- int pil;
- pil = 5;
- if (pdev) {
- switch ((pdev->class >> 16) & 0xff) {
- case PCI_BASE_CLASS_STORAGE:
- pil = 5;
- break;
-
- case PCI_BASE_CLASS_NETWORK:
- pil = 6;
- break;
-
- case PCI_BASE_CLASS_DISPLAY:
- pil = 9;
- break;
-
- case PCI_BASE_CLASS_MULTIMEDIA:
- case PCI_BASE_CLASS_MEMORY:
- case PCI_BASE_CLASS_BRIDGE:
- case PCI_BASE_CLASS_SERIAL:
- pil = 10;
- break;
-
- default:
- pil = 5;
- break;
- };
- }
- BUG_ON(PIL_RESERVED(pil));
-
- return sun4v_build_irq(devhandle, devino, pil, IBF_PCI);
+ return sun4v_build_irq(devhandle, devino);
}
static void pci_sun4v_base_address_update(struct pci_dev *pdev, int resource)
diff --git a/arch/sparc64/kernel/sbus.c b/arch/sparc64/kernel/sbus.c
index 1d6ffdeabd4..8812417247d 100644
--- a/arch/sparc64/kernel/sbus.c
+++ b/arch/sparc64/kernel/sbus.c
@@ -691,36 +691,6 @@ void sbus_set_sbus64(struct sbus_dev *sdev, int bursts)
upa_writeq(val, cfg_reg);
}
-/* SBUS SYSIO INO number to Sparc PIL level. */
-static unsigned char sysio_ino_to_pil[] = {
- 0, 5, 5, 7, 5, 7, 8, 9, /* SBUS slot 0 */
- 0, 5, 5, 7, 5, 7, 8, 9, /* SBUS slot 1 */
- 0, 5, 5, 7, 5, 7, 8, 9, /* SBUS slot 2 */
- 0, 5, 5, 7, 5, 7, 8, 9, /* SBUS slot 3 */
- 5, /* Onboard SCSI */
- 5, /* Onboard Ethernet */
-/*XXX*/ 8, /* Onboard BPP */
- 0, /* Bogon */
- 13, /* Audio */
-/*XXX*/15, /* PowerFail */
- 0, /* Bogon */
- 0, /* Bogon */
- 12, /* Zilog Serial Channels (incl. Keyboard/Mouse lines) */
- 11, /* Floppy */
- 0, /* Spare Hardware (bogon for now) */
- 0, /* Keyboard (bogon for now) */
- 0, /* Mouse (bogon for now) */
- 0, /* Serial (bogon for now) */
- 0, 0, /* Bogon, Bogon */
- 10, /* Timer 0 */
- 11, /* Timer 1 */
- 0, 0, /* Bogon, Bogon */
- 15, /* Uncorrectable SBUS Error */
- 15, /* Correctable SBUS Error */
- 15, /* SBUS Error */
-/*XXX*/ 0, /* Power Management (bogon for now) */
-};
-
/* INO number to IMAP register offset for SYSIO external IRQ's.
* This should conform to both Sunfire/Wildfire server and Fusion
* desktop designs.
@@ -812,21 +782,12 @@ unsigned int sbus_build_irq(void *buscookie, unsigned int ino)
struct sbus_iommu *iommu = sbus->iommu;
unsigned long reg_base = iommu->sbus_control_reg - 0x2000UL;
unsigned long imap, iclr;
- int pil, sbus_level = 0;
-
- pil = sysio_ino_to_pil[ino];
- if (!pil) {
- printk("sbus_irq_build: Bad SYSIO INO[%x]\n", ino);
- panic("Bad SYSIO IRQ translations...");
- }
-
- if (PIL_RESERVED(pil))
- BUG();
+ int sbus_level = 0;
imap = sysio_irq_offsets[ino];
if (imap == ((unsigned long)-1)) {
- prom_printf("get_irq_translations: Bad SYSIO INO[%x] cpu[%d]\n",
- ino, pil);
+ prom_printf("get_irq_translations: Bad SYSIO INO[%x]\n",
+ ino);
prom_halt();
}
imap += reg_base;
@@ -860,7 +821,7 @@ unsigned int sbus_build_irq(void *buscookie, unsigned int ino)
iclr += ((unsigned long)sbus_level - 1UL) * 8UL;
}
- return build_irq(pil, sbus_level, iclr, imap);
+ return build_irq(sbus_level, iclr, imap);
}
/* Error interrupt handling. */
diff --git a/arch/sparc64/kernel/sparc64_ksyms.c b/arch/sparc64/kernel/sparc64_ksyms.c
index 38e569f786d..4ac35dd2088 100644
--- a/arch/sparc64/kernel/sparc64_ksyms.c
+++ b/arch/sparc64/kernel/sparc64_ksyms.c
@@ -125,9 +125,6 @@ EXPORT_SYMBOL(__write_lock);
EXPORT_SYMBOL(__write_unlock);
EXPORT_SYMBOL(__write_trylock);
-/* Hard IRQ locking */
-EXPORT_SYMBOL(synchronize_irq);
-
#if defined(CONFIG_MCOUNT)
extern void _mcount(void);
EXPORT_SYMBOL(_mcount);
@@ -175,10 +172,6 @@ EXPORT_SYMBOL(set_bit);
EXPORT_SYMBOL(clear_bit);
EXPORT_SYMBOL(change_bit);
-EXPORT_SYMBOL(ivector_table);
-EXPORT_SYMBOL(enable_irq);
-EXPORT_SYMBOL(disable_irq);
-
EXPORT_SYMBOL(__flushw_user);
EXPORT_SYMBOL(tlb_type);
diff --git a/arch/sparc64/kernel/sun4v_ivec.S b/arch/sparc64/kernel/sun4v_ivec.S
index b49a68bdda4..49703c3c576 100644
--- a/arch/sparc64/kernel/sun4v_ivec.S
+++ b/arch/sparc64/kernel/sun4v_ivec.S
@@ -5,6 +5,7 @@
#include <asm/cpudata.h>
#include <asm/intr_queue.h>
+#include <asm/pil.h>
.text
.align 32
@@ -102,23 +103,17 @@ sun4v_dev_mondo:
/* Get &ivector_table[IVEC] into %g4. */
sethi %hi(ivector_table), %g4
- sllx %g3, 5, %g3
+ sllx %g3, 3, %g3
or %g4, %lo(ivector_table), %g4
add %g4, %g3, %g4
- /* Load IRQ %pil into %g5. */
- ldub [%g4 + 0x04], %g5
-
/* Insert ivector_table[] entry into __irq_work[] queue. */
- sllx %g5, 2, %g3
- lduw [%g1 + %g3], %g2 /* g2 = irq_work(cpu, pil) */
+ lduw [%g1], %g2 /* g2 = irq_work(cpu) */
stw %g2, [%g4 + 0x00] /* bucket->irq_chain = g2 */
- stw %g4, [%g1 + %g3] /* irq_work(cpu, pil) = bucket */
+ stw %g4, [%g1] /* irq_work(cpu) = bucket */
/* Signal the interrupt by setting (1 << pil) in %softint. */
- mov 1, %g2
- sllx %g2, %g5, %g2
- wr %g2, 0x0, %set_softint
+ wr %g0, 1 << PIL_DEVICE_IRQ, %set_softint
sun4v_dev_mondo_queue_empty:
retry
diff --git a/arch/sparc64/kernel/time.c b/arch/sparc64/kernel/time.c
index e55b5c6ece0..0f00a99927e 100644
--- a/arch/sparc64/kernel/time.c
+++ b/arch/sparc64/kernel/time.c
@@ -457,7 +457,7 @@ static inline void timer_check_rtc(void)
}
}
-static irqreturn_t timer_interrupt(int irq, void *dev_id, struct pt_regs * regs)
+irqreturn_t timer_interrupt(int irq, void *dev_id, struct pt_regs * regs)
{
unsigned long ticks, compare, pstate;
@@ -1020,19 +1020,9 @@ static unsigned long sparc64_init_timers(void)
return clock;
}
-static void sparc64_start_timers(irqreturn_t (*cfunc)(int, void *, struct pt_regs *))
+static void sparc64_start_timers(void)
{
unsigned long pstate;
- int err;
-
- /* Register IRQ handler. */
- err = request_irq(build_irq(0, 0, 0UL, 0UL), cfunc, 0,
- "timer", NULL);
-
- if (err) {
- prom_printf("Serious problem, cannot register TICK_INT\n");
- prom_halt();
- }
/* Guarantee that the following sequences execute
* uninterrupted.
@@ -1116,7 +1106,7 @@ void __init time_init(void)
/* Now that the interpolator is registered, it is
* safe to start the timer ticking.
*/
- sparc64_start_timers(timer_interrupt);
+ sparc64_start_timers();
timer_ticks_per_nsec_quotient =
(((NSEC_PER_SEC << SPARC64_NSEC_PER_CYC_SHIFT) +
diff --git a/arch/sparc64/kernel/traps.c b/arch/sparc64/kernel/traps.c
index 563db528e03..5059cbd4fee 100644
--- a/arch/sparc64/kernel/traps.c
+++ b/arch/sparc64/kernel/traps.c
@@ -2544,7 +2544,9 @@ void __init trap_init(void)
(TRAP_PER_CPU_TSB_HUGE !=
offsetof(struct trap_per_cpu, tsb_huge)) ||
(TRAP_PER_CPU_TSB_HUGE_TEMP !=
- offsetof(struct trap_per_cpu, tsb_huge_temp)))
+ offsetof(struct trap_per_cpu, tsb_huge_temp)) ||
+ (TRAP_PER_CPU_IRQ_WORKLIST !=
+ offsetof(struct trap_per_cpu, irq_worklist)))
trap_per_cpu_offsets_are_bolixed_dave();
if ((TSB_CONFIG_TSB !=
diff --git a/arch/sparc64/kernel/ttable.S b/arch/sparc64/kernel/ttable.S
index 5d901519db5..ee45ca2d7a0 100644
--- a/arch/sparc64/kernel/ttable.S
+++ b/arch/sparc64/kernel/ttable.S
@@ -58,13 +58,11 @@ tl0_irq2: BTRAP(0x42)
tl0_irq3: BTRAP(0x43)
tl0_irq4: BTRAP(0x44)
#endif
-tl0_irq5: TRAP_IRQ(handler_irq, 5) TRAP_IRQ(handler_irq, 6)
-tl0_irq7: TRAP_IRQ(handler_irq, 7) TRAP_IRQ(handler_irq, 8)
-tl0_irq9: TRAP_IRQ(handler_irq, 9) TRAP_IRQ(handler_irq, 10)
-tl0_irq11: TRAP_IRQ(handler_irq, 11) TRAP_IRQ(handler_irq, 12)
-tl0_irq13: TRAP_IRQ(handler_irq, 13)
+tl0_irq5: TRAP_IRQ(handler_irq, 5)
+tl0_irq6: BTRAP(0x46) BTRAP(0x47) BTRAP(0x48) BTRAP(0x49)
+tl0_irq10: BTRAP(0x4a) BTRAP(0x4b) BTRAP(0x4c) BTRAP(0x4d)
#ifndef CONFIG_SMP
-tl0_irq14: TRAP_IRQ(handler_irq, 14)
+tl0_irq14: TRAP_IRQ(timer_irq, 14)
#else
tl0_irq14: TICK_SMP_IRQ
#endif
generated by cgit (git 2.34.1) at 2024-11-12 22:23:35 +0000