diff options
Diffstat (limited to 'arch/sh/boards/dreamcast')
| -rw-r--r-- | arch/sh/boards/dreamcast/Makefile | 6 | ||||
| -rw-r--r-- | arch/sh/boards/dreamcast/irq.c | 160 | ||||
| -rw-r--r-- | arch/sh/boards/dreamcast/rtc.c | 81 | ||||
| -rw-r--r-- | arch/sh/boards/dreamcast/setup.c | 83 |
4 files changed, 330 insertions, 0 deletions
diff --git a/arch/sh/boards/dreamcast/Makefile b/arch/sh/boards/dreamcast/Makefile new file mode 100644 index 00000000000..7b97546c7e5 --- /dev/null +++ b/arch/sh/boards/dreamcast/Makefile @@ -0,0 +1,6 @@ +# +# Makefile for the Sega Dreamcast specific parts of the kernel +# + +obj-y := setup.o irq.o rtc.o + diff --git a/arch/sh/boards/dreamcast/irq.c b/arch/sh/boards/dreamcast/irq.c new file mode 100644 index 00000000000..b10a6b11c03 --- /dev/null +++ b/arch/sh/boards/dreamcast/irq.c @@ -0,0 +1,160 @@ +/* + * arch/sh/boards/dreamcast/irq.c + * + * Holly IRQ support for the Sega Dreamcast. + * + * Copyright (c) 2001, 2002 M. R. Brown <mrbrown@0xd6.org> + * + * This file is part of the LinuxDC project (www.linuxdc.org) + * Released under the terms of the GNU GPL v2.0 + */ + +#include <linux/irq.h> + +#include <asm/io.h> +#include <asm/irq.h> +#include <asm/dreamcast/sysasic.h> + +/* Dreamcast System ASIC Hardware Events - + + The Dreamcast's System ASIC (a.k.a. Holly) is responsible for receiving + hardware events from system peripherals and triggering an SH7750 IRQ. + Hardware events can trigger IRQs 13, 11, or 9 depending on which bits are + set in the Event Mask Registers (EMRs). When a hardware event is + triggered, it's corresponding bit in the Event Status Registers (ESRs) + is set, and that bit should be rewritten to the ESR to acknowledge that + event. + + There are three 32-bit ESRs located at 0xa05f8900 - 0xa05f6908. Event + types can be found in include/asm-sh/dc_sysasic.h. There are three groups + of EMRs that parallel the ESRs. Each EMR group corresponds to an IRQ, so + 0xa05f6910 - 0xa05f6918 triggers IRQ 13, 0xa05f6920 - 0xa05f6928 triggers + IRQ 11, and 0xa05f6930 - 0xa05f6938 triggers IRQ 9. + + In the kernel, these events are mapped to virtual IRQs so that drivers can + respond to them as they would a normal interrupt. In order to keep this + mapping simple, the events are mapped as: + + 6900/6910 - Events 0-31, IRQ 13 + 6904/6924 - Events 32-63, IRQ 11 + 6908/6938 - Events 64-95, IRQ 9 + +*/ + +#define ESR_BASE 0x005f6900 /* Base event status register */ +#define EMR_BASE 0x005f6910 /* Base event mask register */ + +/* Helps us determine the EMR group that this event belongs to: 0 = 0x6910, + 1 = 0x6920, 2 = 0x6930; also determine the event offset */ +#define LEVEL(event) (((event) - HW_EVENT_IRQ_BASE) / 32) + +/* Return the hardware event's bit positon within the EMR/ESR */ +#define EVENT_BIT(event) (((event) - HW_EVENT_IRQ_BASE) & 31) + +/* For each of these *_irq routines, the IRQ passed in is the virtual IRQ + (logically mapped to the corresponding bit for the hardware event). */ + +/* Disable the hardware event by masking its bit in its EMR */ +static inline void disable_systemasic_irq(unsigned int irq) +{ + unsigned long flags; + __u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2); + __u32 mask; + + local_irq_save(flags); + mask = inl(emr); + mask &= ~(1 << EVENT_BIT(irq)); + outl(mask, emr); + local_irq_restore(flags); +} + +/* Enable the hardware event by setting its bit in its EMR */ +static inline void enable_systemasic_irq(unsigned int irq) +{ + unsigned long flags; + __u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2); + __u32 mask; + + local_irq_save(flags); + mask = inl(emr); + mask |= (1 << EVENT_BIT(irq)); + outl(mask, emr); + local_irq_restore(flags); +} + +/* Acknowledge a hardware event by writing its bit back to its ESR */ +static void ack_systemasic_irq(unsigned int irq) +{ + __u32 esr = ESR_BASE + (LEVEL(irq) << 2); + disable_systemasic_irq(irq); + outl((1 << EVENT_BIT(irq)), esr); +} + +/* After a IRQ has been ack'd and responded to, it needs to be renabled */ +static void end_systemasic_irq(unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) + enable_systemasic_irq(irq); +} + +static unsigned int startup_systemasic_irq(unsigned int irq) +{ + enable_systemasic_irq(irq); + + return 0; +} + +static void shutdown_systemasic_irq(unsigned int irq) +{ + disable_systemasic_irq(irq); +} + +struct hw_interrupt_type systemasic_int = { + .typename = "System ASIC", + .startup = startup_systemasic_irq, + .shutdown = shutdown_systemasic_irq, + .enable = enable_systemasic_irq, + .disable = disable_systemasic_irq, + .ack = ack_systemasic_irq, + .end = end_systemasic_irq, +}; + +/* + * Map the hardware event indicated by the processor IRQ to a virtual IRQ. + */ +int systemasic_irq_demux(int irq) +{ + __u32 emr, esr, status, level; + __u32 j, bit; + + switch (irq) { + case 13: + level = 0; + break; + case 11: + level = 1; + break; + case 9: + level = 2; + break; + default: + return irq; + } + emr = EMR_BASE + (level << 4) + (level << 2); + esr = ESR_BASE + (level << 2); + + /* Mask the ESR to filter any spurious, unwanted interrtupts */ + status = inl(esr); + status &= inl(emr); + + /* Now scan and find the first set bit as the event to map */ + for (bit = 1, j = 0; j < 32; bit <<= 1, j++) { + if (status & bit) { + irq = HW_EVENT_IRQ_BASE + j + (level << 5); + return irq; + } + } + + /* Not reached */ + return irq; +} diff --git a/arch/sh/boards/dreamcast/rtc.c b/arch/sh/boards/dreamcast/rtc.c new file mode 100644 index 00000000000..379de162913 --- /dev/null +++ b/arch/sh/boards/dreamcast/rtc.c @@ -0,0 +1,81 @@ +/* arch/sh/kernel/rtc-aica.c + * + * Dreamcast AICA RTC routines. + * + * Copyright (c) 2001, 2002 M. R. Brown <mrbrown@0xd6.org> + * Copyright (c) 2002 Paul Mundt <lethal@chaoticdreams.org> + * + * Released under the terms of the GNU GPL v2.0. + * + */ + +#include <linux/time.h> + +#include <asm/io.h> + +extern void (*rtc_get_time)(struct timespec *); +extern int (*rtc_set_time)(const time_t); + +/* The AICA RTC has an Epoch of 1/1/1950, so we must subtract 20 years (in + seconds to get the standard Unix Epoch when getting the time, and add 20 + years when setting the time. */ +#define TWENTY_YEARS ((20 * 365LU + 5) * 86400) + +/* The AICA RTC is represented by a 32-bit seconds counter stored in 2 16-bit + registers.*/ +#define AICA_RTC_SECS_H 0xa0710000 +#define AICA_RTC_SECS_L 0xa0710004 + +/** + * aica_rtc_gettimeofday - Get the time from the AICA RTC + * @ts: pointer to resulting timespec + * + * Grabs the current RTC seconds counter and adjusts it to the Unix Epoch. + */ +void aica_rtc_gettimeofday(struct timespec *ts) { + unsigned long val1, val2; + + do { + val1 = ((ctrl_inl(AICA_RTC_SECS_H) & 0xffff) << 16) | + (ctrl_inl(AICA_RTC_SECS_L) & 0xffff); + + val2 = ((ctrl_inl(AICA_RTC_SECS_H) & 0xffff) << 16) | + (ctrl_inl(AICA_RTC_SECS_L) & 0xffff); + } while (val1 != val2); + + ts->tv_sec = val1 - TWENTY_YEARS; + + /* Can't get nanoseconds with just a seconds counter. */ + ts->tv_nsec = 0; +} + +/** + * aica_rtc_settimeofday - Set the AICA RTC to the current time + * @secs: contains the time_t to set + * + * Adjusts the given @tv to the AICA Epoch and sets the RTC seconds counter. + */ +int aica_rtc_settimeofday(const time_t secs) { + unsigned long val1, val2; + unsigned long adj = secs + TWENTY_YEARS; + + do { + ctrl_outl((adj & 0xffff0000) >> 16, AICA_RTC_SECS_H); + ctrl_outl((adj & 0xffff), AICA_RTC_SECS_L); + + val1 = ((ctrl_inl(AICA_RTC_SECS_H) & 0xffff) << 16) | + (ctrl_inl(AICA_RTC_SECS_L) & 0xffff); + + val2 = ((ctrl_inl(AICA_RTC_SECS_H) & 0xffff) << 16) | + (ctrl_inl(AICA_RTC_SECS_L) & 0xffff); + } while (val1 != val2); + + return 0; +} + +void aica_time_init(void) +{ + rtc_get_time = aica_rtc_gettimeofday; + rtc_set_time = aica_rtc_settimeofday; +} + diff --git a/arch/sh/boards/dreamcast/setup.c b/arch/sh/boards/dreamcast/setup.c new file mode 100644 index 00000000000..55dece35cde --- /dev/null +++ b/arch/sh/boards/dreamcast/setup.c @@ -0,0 +1,83 @@ +/* + * arch/sh/boards/dreamcast/setup.c + * + * Hardware support for the Sega Dreamcast. + * + * Copyright (c) 2001, 2002 M. R. Brown <mrbrown@linuxdc.org> + * Copyright (c) 2002, 2003, 2004 Paul Mundt <lethal@linux-sh.org> + * + * This file is part of the LinuxDC project (www.linuxdc.org) + * + * Released under the terms of the GNU GPL v2.0. + * + * This file originally bore the message (with enclosed-$): + * Id: setup_dc.c,v 1.5 2001/05/24 05:09:16 mrbrown Exp + * SEGA Dreamcast support + */ + +#include <linux/sched.h> +#include <linux/kernel.h> +#include <linux/param.h> +#include <linux/interrupt.h> +#include <linux/init.h> +#include <linux/irq.h> +#include <linux/device.h> + +#include <asm/io.h> +#include <asm/irq.h> +#include <asm/machvec.h> +#include <asm/machvec_init.h> +#include <asm/mach/sysasic.h> + +extern struct hw_interrupt_type systemasic_int; +/* XXX: Move this into it's proper header. */ +extern void (*board_time_init)(void); +extern void aica_time_init(void); +extern int gapspci_init(void); +extern int systemasic_irq_demux(int); + +void *dreamcast_consistent_alloc(struct device *, size_t, dma_addr_t *, int); +int dreamcast_consistent_free(struct device *, size_t, void *, dma_addr_t); + +const char *get_system_type(void) +{ + return "Sega Dreamcast"; +} + +struct sh_machine_vector mv_dreamcast __initmv = { + .mv_nr_irqs = NR_IRQS, + + .mv_irq_demux = systemasic_irq_demux, + +#ifdef CONFIG_PCI + .mv_consistent_alloc = dreamcast_consistent_alloc, + .mv_consistent_free = dreamcast_consistent_free, +#endif +}; +ALIAS_MV(dreamcast) + +int __init platform_setup(void) +{ + int i; + + /* Mask all hardware events */ + /* XXX */ + + /* Acknowledge any previous events */ + /* XXX */ + + __set_io_port_base(0xa0000000); + + /* Assign all virtual IRQs to the System ASIC int. handler */ + for (i = HW_EVENT_IRQ_BASE; i < HW_EVENT_IRQ_MAX; i++) + irq_desc[i].handler = &systemasic_int; + + board_time_init = aica_time_init; + +#ifdef CONFIG_PCI + if (gapspci_init() < 0) + printk(KERN_WARNING "GAPSPCI was not detected.\n"); +#endif + + return 0; +} |