kernel-crypto.git - User-space crypto API development for Linux

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author	Ralf Baechle <ralf@linux-mips.org>	2006-01-23 16:15:30 +0000
committer	Ralf Baechle <ralf@linux-mips.org>	2006-02-07 13:30:23 +0000
commit	4feb8f8f4589d1cb1594e344c9672ec40f627ab4 (patch)
tree	21f603c3537c2533b68ce1e7f3adfa7b950dbdbc /include/linux/smb.h
parent	c03bc121212ecb36120b118a94c1b91a2e07b7b2 (diff)
download	kernel-crypto-4feb8f8f4589d1cb1594e344c9672ec40f627ab4.tar.gz kernel-crypto-4feb8f8f4589d1cb1594e344c9672ec40f627ab4.tar.xz kernel-crypto-4feb8f8f4589d1cb1594e344c9672ec40f627ab4.zip

[MIPS] Bullet proof uaccess.h against 4.0.1 miss-compilation.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Diffstat (limited to 'include/linux/smb.h')

0 files changed, 0 insertions, 0 deletions

/* * (C) Copyright 2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ /* * board/config.h - configuration options, board specific */ /* Yoo. Jonghoon, IPone, yooth@ipone.co.kr * U-BOOT port on RPXlite board */ /* * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn * U-BOOT port on RPXlite DW version board--RPXlite_DW * June 8 ,2004 */ #ifndef __CONFIG_H #define __CONFIG_H /* * High Level Configuration Options * (easy to change) */ /* #define DEBUG 1 */ /* #ifdef DEPLOYMENT 1 */ #undef CONFIG_MPC860 #define CONFIG_MPC823 1 /* This is a MPC823e CPU. */ #define CONFIG_RPXLITE 1 /* RPXlite DW version board */ #ifdef CONFIG_LCD /* with LCD controller ? */ #define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/ #endif #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ #undef CONFIG_8xx_CONS_SMC2 #undef CONFIG_8xx_CONS_NONE #define CONFIG_BAUDRATE 9600 /* console default baudrate = 9600bps */ #ifdef DEBUG #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ #else #define CONFIG_BOOTDELAY 6 /* autoboot after 6 seconds */ #ifdef DEPLOYMENT #define CONFIG_BOOT_RETRY_TIME -1 #define CONFIG_AUTOBOOT_KEYED #define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds (stop with 'st')...\n" #define CONFIG_AUTOBOOT_STOP_STR "st" #define CONFIG_ZERO_BOOTDELAY_CHECK #define CONFIG_RESET_TO_RETRY 1 #define CONFIG_BOOT_RETRY_MIN 1 #endif /* DEPLOYMENT */ #endif /* DEBUG */ /* pre-boot commands */ #define CONFIG_PREBOOT "setenv stdout serial;setenv stdin serial" #undef CONFIG_BOOTARGS #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "nfsargs=setenv bootargs console=tty0 console=ttyS0,9600 " \ "root=/dev/nfs rw nfsroot=$(serverip):$(rootpath)\0" \ "ramargs=setenv bootargs console=tty0 root=/dev/ram rw\0" \ "addip=setenv bootargs $(bootargs) " \ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ ":$(hostname):$(netdev):off panic=1\0" \ "flash_nfs=run nfsargs addip;" \ "bootm $(kernel_addr)\0" \ "flash_self=run ramargs addip;" \ "bootm $(kernel_addr) $(ramdisk_addr)\0" \ "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ "gatewayip=172.16.115.254\0" \ "netmask=255.255.255.0\0" \ "kernel_addr=ff040000\0" \ "ramdisk_addr=ff200000\0" \ "ku=era $(kernel_addr) ff1fffff;cp.b 100000 $(kernel_addr) " \ "$(filesize);md $(kernel_addr);" \ "echo kernel updating finished\0" \ "uu=protect off 1:0-4;era 1:0-4;cp.b 100000 ff000000 " \ "$(filesize);md ff000000;" \ "echo u-boot updating finished\0" \ "eu=protect off 1:6;era 1:6;reset\0" \ "lcd=setenv stdout lcd;setenv stdin lcd\0" \ "ser=setenv stdout serial;setenv stdin serial\0" \ "verify=no" #define CONFIG_BOOTCOMMAND "run flash_self" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ #undef CONFIG_WATCHDOG /* watchdog disabled */ #undef CONFIG_STATUS_LED /* disturbs display. Status LED disabled. */ #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "u-boot>" /* Monitor Command Prompt */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ #define CFG_MAXARGS 16 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_MEMTEST_START 0x0040000 /* memtest works on */ #define CFG_MEMTEST_END 0x00C0000 /* 4 ... 12 MB in DRAM */ #define CFG_LOAD_ADDR 0x100000 /* default load address */ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* * Low Level Configuration Settings * (address mappings, register initial values, etc.) * You should know what you are doing if you make changes here. */ /*----------------------------------------------------------------------- * Internal Memory Mapped Register */ #define CFG_IMMR 0xFA200000 /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ #define CFG_INIT_RAM_ADDR CFG_IMMR #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) * Please note that CFG_SDRAM_BASE _must_ start at 0 */ #define CFG_SDRAM_BASE 0x00000000 #define CFG_FLASH_BASE 0xFF000000 #if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE) #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #else #define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ #endif #define CFG_MONITOR_BASE 0xFF000000 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /*----------------------------------------------------------------------- * FLASH organization */ #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ #define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ #ifdef CFG_ENV_IS_IN_NVRAM #define CFG_ENV_ADDR 0xFA000100 #define CFG_ENV_SIZE 0x1000 #else #define CFG_ENV_IS_IN_FLASH #define CFG_ENV_OFFSET 0x30000 /* Offset of Environment Sector */ #define CFG_ENV_SIZE 0x8000 /* Total Size of Environment Sector */ #endif /* CFG_ENV_IS_IN_NVRAM */ #define CFG_RESET_ADDRESS ((ulong)((((immap_t *)CFG_IMMR)->im_clkrst.res))) /*----------------------------------------------------------------------- * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif /*----------------------------------------------------------------------- * SYPCR - System Protection Control 32-bit 12-35 * SYPCR can only be written once after reset! *----------------------------------------------------------------------- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze */ #if defined(CONFIG_WATCHDOG) #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) #else #define CFG_SYPCR (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) #endif /* We can get SYPCR: 0xFFFF0689. */ /*----------------------------------------------------------------------- * SIUMCR - SIU Module Configuration 32-bit 12-30 *----------------------------------------------------------------------- * PCMCIA config., multi-function pin tri-state */ #define CFG_SIUMCR (SIUMCR_MLRC10) /* SIUMCR:0x00000800 */ /*--------------------------------------------------------------------- * TBSCR - Time Base Status and Control 16-bit 12-16 *--------------------------------------------------------------------- * Clear Reference Interrupt Status, Timebase freezing enabled */ #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE) /* TBSCR: 0x00C3 [SAM] */ /*----------------------------------------------------------------------- * RTCSC - Real-Time Clock Status and Control Register 16-bit 12-18 *----------------------------------------------------------------------- * [RTC enabled but not stopped on FRZ] */ #define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTE) /* RTCSC:0x00C1 */ /*----------------------------------------------------------------------- * PISCR - Periodic Interrupt Status and Control 16-bit 12-23 *----------------------------------------------------------------------- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled * [Periodic timer enabled,Periodic timer interrupt disable. ] */ #define CFG_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) /* PISCR:0x0083 */ /*----------------------------------------------------------------------- * PLPRCR - PLL, Low-Power, and Reset Control Register 32-bit 5-7 *----------------------------------------------------------------------- * Reset PLL lock status sticky bit, timer expired status bit and timer * interrupt status bit */ /* up to 64 MHz we use a 1:2 clock */ #if defined(RPXlite_64MHz) #define CFG_PLPRCR ( (7 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS ) /*PLPRCR: 0x00700000. */ #else #define CFG_PLPRCR ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS ) #endif /*----------------------------------------------------------------------- * SCCR - System Clock and reset Control Register 5-3


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