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| author | Borislav Petkov <borislav.petkov@amd.com> | 2010-02-18 19:37:14 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@suse.de> | 2010-04-26 07:47:57 -0700 |
| commit | faef0b851da169e44a842ab3b257a84857ac8f7f (patch) | |
| tree | b68de1170b89b2155e8fcd76393ec34f3c66deb9 /include/linux/dm-ioctl.h | |
| parent | f8b1a072d4f260c203eb500beb70a1e1c2ff8689 (diff) | |
| download | kernel-crypto-faef0b851da169e44a842ab3b257a84857ac8f7f.tar.gz kernel-crypto-faef0b851da169e44a842ab3b257a84857ac8f7f.tar.xz kernel-crypto-faef0b851da169e44a842ab3b257a84857ac8f7f.zip | |
x86, cacheinfo: Enable L3 CID only on AMD
commit cb19060abfdecac0d1eb2d2f0e7d6b7a3f8bc4f4 upstream.
Final stage linking can fail with
arch/x86/built-in.o: In function `store_cache_disable':
intel_cacheinfo.c:(.text+0xc509): undefined reference to `amd_get_nb_id'
arch/x86/built-in.o: In function `show_cache_disable':
intel_cacheinfo.c:(.text+0xc7d3): undefined reference to `amd_get_nb_id'
when CONFIG_CPU_SUP_AMD is not enabled because the amd_get_nb_id
helper is defined in AMD-specific code but also used in generic code
(intel_cacheinfo.c). Reorganize the L3 cache index disable code under
CONFIG_CPU_SUP_AMD since it is AMD-only anyway.
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
LKML-Reference: <20100218184210.GF20473@aftab>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'include/linux/dm-ioctl.h')
0 files changed, 0 insertions, 0 deletions