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author | Ingo Molnar <mingo@elte.hu> | 2008-07-16 00:29:07 +0200 |
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committer | Ingo Molnar <mingo@elte.hu> | 2008-07-16 00:29:07 +0200 |
commit | 82638844d9a8581bbf33201cc209a14876eca167 (patch) | |
tree | 961d7f9360194421a71aa644a9d0c176a960ce49 /include/asm-arm/assembler.h | |
parent | 9982fbface82893e77d211fbabfbd229da6bdde6 (diff) | |
parent | 63cf13b77ab785e87c867defa8545e6d4a989774 (diff) | |
download | kernel-crypto-82638844d9a8581bbf33201cc209a14876eca167.tar.gz kernel-crypto-82638844d9a8581bbf33201cc209a14876eca167.tar.xz kernel-crypto-82638844d9a8581bbf33201cc209a14876eca167.zip |
Merge branch 'linus' into cpus4096
Conflicts:
arch/x86/xen/smp.c
kernel/sched_rt.c
net/iucv/iucv.c
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'include/asm-arm/assembler.h')
-rw-r--r-- | include/asm-arm/assembler.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/include/asm-arm/assembler.h b/include/asm-arm/assembler.h index fce83282082..911393b2c6f 100644 --- a/include/asm-arm/assembler.h +++ b/include/asm-arm/assembler.h @@ -56,6 +56,21 @@ #endif /* + * This can be used to enable code to cacheline align the destination + * pointer when bulk writing to memory. Experiments on StrongARM and + * XScale didn't show this a worthwhile thing to do when the cache is not + * set to write-allocate (this would need further testing on XScale when WA + * is used). + * + * On Feroceon there is much to gain however, regardless of cache mode. + */ +#ifdef CONFIG_CPU_FEROCEON +#define CALGN(code...) code +#else +#define CALGN(code...) +#endif + +/* * Enable and disable interrupts */ #if __LINUX_ARM_ARCH__ >= 6 |