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authorBen Dooks <ben-linux@fluff.org>2007-06-06 09:51:51 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2007-06-11 09:09:15 +0100
commitc362aecdb51ecb364d427a9b947fd2dfbd4cb86a (patch)
tree4e88fb0552ff6578c1018924e9ed735056d18ef5 /include/asm-arm/arch-s3c2410
parent5d4cae5fe2ea1a0974962e2c49dca5c9c4b14cc0 (diff)
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[ARM] 4442/1: OSIRIS: Fix CPLD register definitions
Fix the CPLD register definitions to correctly mirror the documentation Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm/arch-s3c2410')
-rw-r--r--include/asm-arm/arch-s3c2410/osiris-cpld.h14
-rw-r--r--include/asm-arm/arch-s3c2410/osiris-map.h19
2 files changed, 19 insertions, 14 deletions
diff --git a/include/asm-arm/arch-s3c2410/osiris-cpld.h b/include/asm-arm/arch-s3c2410/osiris-cpld.h
index 3b6498468d6..a3253e979ef 100644
--- a/include/asm-arm/arch-s3c2410/osiris-cpld.h
+++ b/include/asm-arm/arch-s3c2410/osiris-cpld.h
@@ -14,12 +14,14 @@
#ifndef __ASM_ARCH_OSIRISCPLD_H
#define __ASM_ARCH_OSIRISCPLD_H
-/* CTRL1 - NAND WP control */
+/* CTRL0 - NAND WP control */
-#define OSIRIS_CTRL1_NANDSEL (0x3)
-#define OSIRIS_CTRL1_BOOT_INT (1<<3)
-#define OSIRIS_CTRL1_PCMCIA (1<<4)
-#define OSIRIS_CTRL1_PCMCIA_nWAIT (1<<6)
-#define OSIRIS_CTRL1_PCMCIA_nIOIS16 (1<<7)
+#define OSIRIS_CTRL0_NANDSEL (0x3)
+#define OSIRIS_CTRL0_BOOT_INT (1<<3)
+#define OSIRIS_CTRL0_PCMCIA (1<<4)
+#define OSIRIS_CTRL0_PCMCIA_nWAIT (1<<6)
+#define OSIRIS_CTRL0_PCMCIA_nIOIS16 (1<<7)
+
+#define OSIRIS_ID_REVMASK (0x7)
#endif /* __ASM_ARCH_OSIRISCPLD_H */
diff --git a/include/asm-arm/arch-s3c2410/osiris-map.h b/include/asm-arm/arch-s3c2410/osiris-map.h
index a14164dfa52..b5c74d2b9aa 100644
--- a/include/asm-arm/arch-s3c2410/osiris-map.h
+++ b/include/asm-arm/arch-s3c2410/osiris-map.h
@@ -24,16 +24,19 @@
/* we put the CPLD registers next, to get them out of the way */
-#define OSIRIS_VA_CTRL1 OSIRIS_IOADDR(0x00000000)
-#define OSIRIS_PA_CTRL1 (OSIRIS_PA_CPLD)
+#define OSIRIS_VA_CTRL0 OSIRIS_IOADDR(0x00000000)
+#define OSIRIS_PA_CTRL0 (OSIRIS_PA_CPLD)
-#define OSIRIS_VA_CTRL2 OSIRIS_IOADDR(0x00100000)
-#define OSIRIS_PA_CTRL2 (OSIRIS_PA_CPLD + (1<<23))
+#define OSIRIS_VA_CTRL1 OSIRIS_IOADDR(0x00100000)
+#define OSIRIS_PA_CTRL1 (OSIRIS_PA_CPLD + (1<<23))
-#define OSIRIS_VA_CTRL3 OSIRIS_IOADDR(0x00200000)
-#define OSIRIS_PA_CTRL3 (OSIRIS_PA_CPLD + (2<<23))
+#define OSIRIS_VA_CTRL2 OSIRIS_IOADDR(0x00200000)
+#define OSIRIS_PA_CTRL2 (OSIRIS_PA_CPLD + (2<<23))
-#define OSIRIS_VA_CTRL4 OSIRIS_IOADDR(0x00300000)
-#define OSIRIS_PA_CTRL4 (OSIRIS_PA_CPLD + (3<<23))
+#define OSIRIS_VA_CTRL3 OSIRIS_IOADDR(0x00300000)
+#define OSIRIS_PA_CTRL3 (OSIRIS_PA_CPLD + (2<<23))
+
+#define OSIRIS_VA_IDREG OSIRIS_IOADDR(0x00700000)
+#define OSIRIS_PA_IDREG (OSIRIS_PA_CPLD + (7<<23))
#endif /* __ASM_ARCH_OSIRISMAP_H */