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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2010-04-22 18:24:06 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2010-04-22 18:24:06 -0700 |
| commit | 7db2ccddd112d8b4b0d0dd7f309ebd8b39373fbb (patch) | |
| tree | 23b2986db5c47a507039660091cd737506282b4a /drivers/gpu/drm/i915/i915_reg.h | |
| parent | a2b297ff56b9bad251d11a476880a5e4614cd92f (diff) | |
| parent | e552eb7038a36d9b18860f525aa02875e313fe16 (diff) | |
| download | kernel-crypto-7db2ccddd112d8b4b0d0dd7f309ebd8b39373fbb.tar.gz kernel-crypto-7db2ccddd112d8b4b0d0dd7f309ebd8b39373fbb.tar.xz kernel-crypto-7db2ccddd112d8b4b0d0dd7f309ebd8b39373fbb.zip | |
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel:
drm/i915: use PIPE_CONTROL instruction on Ironlake and Sandy Bridge
drm/i915: cleanup FBC buffers at unload time
drm/i915: fix tiling limits for i915 class hw v2
drm/i915: set DIDL using the ACPI video output device _ADR method return.
drm/i915: Fix 82854 PCI ID, and treat it like other 85X
drm/i915: Attempt to fix watermark setup on 85x (v2)
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index cbbf59f56df..4cbc5210fd3 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -230,6 +230,16 @@ #define ASYNC_FLIP (1<<22) #define DISPLAY_PLANE_A (0<<20) #define DISPLAY_PLANE_B (1<<20) +#define GFX_OP_PIPE_CONTROL ((0x3<<29)|(0x3<<27)|(0x2<<24)|2) +#define PIPE_CONTROL_QW_WRITE (1<<14) +#define PIPE_CONTROL_DEPTH_STALL (1<<13) +#define PIPE_CONTROL_WC_FLUSH (1<<12) +#define PIPE_CONTROL_IS_FLUSH (1<<11) /* MBZ on Ironlake */ +#define PIPE_CONTROL_TC_FLUSH (1<<10) /* GM45+ only */ +#define PIPE_CONTROL_ISP_DIS (1<<9) +#define PIPE_CONTROL_NOTIFY (1<<8) +#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */ +#define PIPE_CONTROL_STALL_EN (1<<1) /* in addr word, Ironlake+ only */ /* * Fence registers @@ -241,7 +251,7 @@ #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) #define I830_FENCE_PITCH_SHIFT 4 #define I830_FENCE_REG_VALID (1<<0) -#define I915_FENCE_MAX_PITCH_VAL 0x10 +#define I915_FENCE_MAX_PITCH_VAL 4 #define I830_FENCE_MAX_PITCH_VAL 6 #define I830_FENCE_MAX_SIZE_VAL (1<<8) @@ -2285,6 +2295,7 @@ #define DEIER 0x4400c /* GT interrupt */ +#define GT_PIPE_NOTIFY (1 << 4) #define GT_SYNC_STATUS (1 << 2) #define GT_USER_INTERRUPT (1 << 0) |