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| author | Peter Zijlstra <a.p.zijlstra@chello.nl> | 2009-03-13 12:21:30 +0100 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2009-04-06 09:29:32 +0200 |
| commit | 60b3df9c1e24a18aabb412da9905208c5f04ebea (patch) | |
| tree | 2c132d1a82648b176f8662cea32f51c208517dd5 /arch/x86 | |
| parent | 755642322aa66fbc5421a35fd3e1733f73e20083 (diff) | |
| download | kernel-crypto-60b3df9c1e24a18aabb412da9905208c5f04ebea.tar.gz kernel-crypto-60b3df9c1e24a18aabb412da9905208c5f04ebea.tar.xz kernel-crypto-60b3df9c1e24a18aabb412da9905208c5f04ebea.zip | |
perf_counter: add comment to barrier
We need to ensure the enabled=0 write happens before we
start disabling the actual counters, so that a pcm_amd_enable()
will not enable one underneath us.
I think the race is impossible anyway, we always balance the
ops within any one context and perform enable() with IRQs disabled.
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86')
| -rw-r--r-- | arch/x86/kernel/cpu/perf_counter.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/x86/kernel/cpu/perf_counter.c b/arch/x86/kernel/cpu/perf_counter.c index 1cedc3468ce..a2e3b76bfdc 100644 --- a/arch/x86/kernel/cpu/perf_counter.c +++ b/arch/x86/kernel/cpu/perf_counter.c @@ -247,6 +247,10 @@ static u64 pmc_amd_save_disable_all(void) enabled = cpuc->enabled; cpuc->enabled = 0; + /* + * ensure we write the disable before we start disabling the + * counters proper, so that pcm_amd_enable() does the right thing. + */ barrier(); for (idx = 0; idx < nr_counters_generic; idx++) { |