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authorDavid Gibson <david@gibson.dropbear.id.au>2007-08-14 13:52:42 +1000
committerPaul Mackerras <paulus@samba.org>2007-08-17 11:02:06 +1000
commit553fdff633b1cb8cfccf554768444c5580a8d7f7 (patch)
tree6d87847e2ee77bb60ada7c3dee2158af93352a7b /arch/powerpc/sysdev
parent868afce21fdadcecc7bde9263321065948508c56 (diff)
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[POWERPC] Improve robustness of the UIC cascade handler
At present the cascade interrupt handler for the UIC (interrupt controller on 4xx embedded chips) will misbehave badly if it is called spuriously - that is if the handler is invoked when no interrupts are asserted in the child UIC. Although spurious interrupts shouldn't happen, it's good to behave robustly if they do. This patch does so by checking for and ignoring spurious interrupts. Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Acked-by: Josh Boyer <jwboyer@linux.vnet.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/powerpc/sysdev')
-rw-r--r--arch/powerpc/sysdev/uic.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/powerpc/sysdev/uic.c b/arch/powerpc/sysdev/uic.c
index 22c219e448d..47180b3fca5 100644
--- a/arch/powerpc/sysdev/uic.c
+++ b/arch/powerpc/sysdev/uic.c
@@ -266,6 +266,9 @@ irqreturn_t uic_cascade(int virq, void *data)
int subvirq;
msr = mfdcr(uic->dcrbase + UIC_MSR);
+ if (!msr) /* spurious interrupt */
+ return IRQ_HANDLED;
+
src = 32 - ffs(msr);
subvirq = irq_linear_revmap(uic->irqhost, src);