diff options
author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2005-12-14 13:10:10 +1100 |
---|---|---|
committer | Paul Mackerras <paulus@samba.org> | 2006-01-09 15:03:17 +1100 |
commit | 1beb6a7d6cbed3ac03500ce9b5b9bb632c512039 (patch) | |
tree | 727aa76da5a82fca449dadf3cebbadc414ad6555 /arch/powerpc/platforms/maple | |
parent | cd0c7f06803be06a5cf4564aa5a900f4b6aea603 (diff) | |
download | kernel-crypto-1beb6a7d6cbed3ac03500ce9b5b9bb632c512039.tar.gz kernel-crypto-1beb6a7d6cbed3ac03500ce9b5b9bb632c512039.tar.xz kernel-crypto-1beb6a7d6cbed3ac03500ce9b5b9bb632c512039.zip |
[PATCH] powerpc: Experimental support for new G5 Macs (#2)
This adds some very basic support for the new machines, including the
Quad G5 (tested), and other new dual core based machines and iMac G5
iSight (untested). This is still experimental ! There is no thermal
control yet, there is no proper handing of MSIs, etc.. but it
boots, I have all 4 cores up on my machine. Compared to the previous
version of this patch, this one adds DART IOMMU support for the U4
chipset and thus should work fine on setups with more than 2Gb of RAM.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/powerpc/platforms/maple')
-rw-r--r-- | arch/powerpc/platforms/maple/setup.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/powerpc/platforms/maple/setup.c b/arch/powerpc/platforms/maple/setup.c index 65fe4c166a6..dd73e38bfb7 100644 --- a/arch/powerpc/platforms/maple/setup.c +++ b/arch/powerpc/platforms/maple/setup.c @@ -195,7 +195,7 @@ static void __init maple_init_early(void) /* Setup interrupt mapping options */ ppc64_interrupt_controller = IC_OPEN_PIC; - iommu_init_early_u3(); + iommu_init_early_dart(); DBG(" <- maple_init_early\n"); } @@ -257,7 +257,7 @@ static int __init maple_probe(int platform) * occupies having to be broken up so the DART itself is not * part of the cacheable linar mapping */ - alloc_u3_dart_table(); + alloc_dart_table(); return 1; } |