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| author | Takashi Iwai <tiwai@suse.de> | 2009-05-04 16:05:23 +0200 |
|---|---|---|
| committer | Takashi Iwai <tiwai@suse.de> | 2009-05-04 16:05:23 +0200 |
| commit | 8560b9321f9050968f393ce1ec67e47c1a0bd5cf (patch) | |
| tree | 658ebb20e4fd5dee840f27103b59da367ff473b1 /arch/powerpc/mm | |
| parent | 72e31981a4e91f84c5b5e8994f5d25b1cf22b6cf (diff) | |
| parent | 6574612fbb34c63117581e68f2231ddce027e41e (diff) | |
| download | kernel-crypto-8560b9321f9050968f393ce1ec67e47c1a0bd5cf.tar.gz kernel-crypto-8560b9321f9050968f393ce1ec67e47c1a0bd5cf.tar.xz kernel-crypto-8560b9321f9050968f393ce1ec67e47c1a0bd5cf.zip | |
Merge branch 'fix/asoc' into topic/asoc
Diffstat (limited to 'arch/powerpc/mm')
| -rw-r--r-- | arch/powerpc/mm/hash_utils_64.c | 2 | ||||
| -rw-r--r-- | arch/powerpc/mm/tlb_nohash.c | 1 | ||||
| -rw-r--r-- | arch/powerpc/mm/tlb_nohash_low.S | 14 |
3 files changed, 14 insertions, 3 deletions
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c index db556d25c3a..1ade7eb6ae0 100644 --- a/arch/powerpc/mm/hash_utils_64.c +++ b/arch/powerpc/mm/hash_utils_64.c @@ -753,7 +753,7 @@ void __init early_init_mmu(void) } #ifdef CONFIG_SMP -void __init early_init_mmu_secondary(void) +void __cpuinit early_init_mmu_secondary(void) { /* Initialize hash table for that CPU */ if (!firmware_has_feature(FW_FEATURE_LPAR)) diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c index 7af72970fae..ad2eb4d34dd 100644 --- a/arch/powerpc/mm/tlb_nohash.c +++ b/arch/powerpc/mm/tlb_nohash.c @@ -125,7 +125,6 @@ static void do_flush_tlb_page_ipi(void *param) void flush_tlb_mm(struct mm_struct *mm) { - cpumask_t cpu_mask; unsigned int pid; preempt_disable(); diff --git a/arch/powerpc/mm/tlb_nohash_low.S b/arch/powerpc/mm/tlb_nohash_low.S index 788b87c36f7..45fed369834 100644 --- a/arch/powerpc/mm/tlb_nohash_low.S +++ b/arch/powerpc/mm/tlb_nohash_low.S @@ -138,7 +138,11 @@ BEGIN_MMU_FTR_SECTION andi. r3,r3,MMUCSR0_TLBFI@l bne 1b MMU_FTR_SECTION_ELSE - PPC_TLBILX_ALL(0,0) + BEGIN_MMU_FTR_SECTION_NESTED(96) + PPC_TLBILX_ALL(0,r3) + MMU_FTR_SECTION_ELSE_NESTED(96) + PPC_TLBILX_ALL_EARLY(0,r3) + ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_TLBILX_EARLY_OPCODE, 96) ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX) msync isync @@ -151,7 +155,11 @@ BEGIN_MMU_FTR_SECTION wrteei 0 mfspr r4,SPRN_MAS6 /* save MAS6 */ mtspr SPRN_MAS6,r3 + BEGIN_MMU_FTR_SECTION_NESTED(96) PPC_TLBILX_PID(0,0) + MMU_FTR_SECTION_ELSE_NESTED(96) + PPC_TLBILX_PID_EARLY(0,0) + ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_TLBILX_EARLY_OPCODE, 96) mtspr SPRN_MAS6,r4 /* restore MAS6 */ wrtee r10 MMU_FTR_SECTION_ELSE @@ -185,7 +193,11 @@ BEGIN_MMU_FTR_SECTION mtspr SPRN_MAS1,r4 tlbwe MMU_FTR_SECTION_ELSE + BEGIN_MMU_FTR_SECTION_NESTED(96) PPC_TLBILX_VA(0,r3) + MMU_FTR_SECTION_ELSE_NESTED(96) + PPC_TLBILX_VA_EARLY(0,r3) + ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_TLBILX_EARLY_OPCODE, 96) ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX) msync isync |