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| author | Martyn Welch <martyn.welch@gefanuc.com> | 2008-11-10 12:31:33 +0000 |
|---|---|---|
| committer | Wim Van Sebroeck <wim@iguana.be> | 2009-01-12 20:08:47 +0000 |
| commit | 6ec9eae67a82a38865af20580e5e0ccd012aca4b (patch) | |
| tree | 62b68f31f6f52dd6785340475b63d9854e456b81 /arch/powerpc/boot/dts/gef_sbc610.dts | |
| parent | 3268b5618f387c6b78b8f8b1190d43380c8170ac (diff) | |
| download | kernel-crypto-6ec9eae67a82a38865af20580e5e0ccd012aca4b.tar.gz kernel-crypto-6ec9eae67a82a38865af20580e5e0ccd012aca4b.tar.xz kernel-crypto-6ec9eae67a82a38865af20580e5e0ccd012aca4b.zip | |
[WATCHDOG] Enable watchdog timer on GE Fanuc's SBC610
Support for the FPGA based watchdog timer on GE Fanuc's SBC610.
This patch enables one of the watchdog timers found on the SBC610. There are
two identical watchdog timers at different offsets in the above mentioned
boards, however the current driver is only capable of supporting one of them.
The watchdog timers are also capable of generating interrupts at a
user-configurable threshold, though support for this operation is currently
not supported by the driver.
Signed-off-by: Martyn Welch <martyn.welch@gefanuc.com>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
Diffstat (limited to 'arch/powerpc/boot/dts/gef_sbc610.dts')
| -rw-r--r-- | arch/powerpc/boot/dts/gef_sbc610.dts | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/gef_sbc610.dts b/arch/powerpc/boot/dts/gef_sbc610.dts index 9708b3423bb..e78c355c7ba 100644 --- a/arch/powerpc/boot/dts/gef_sbc610.dts +++ b/arch/powerpc/boot/dts/gef_sbc610.dts @@ -88,6 +88,21 @@ compatible = "gef,fpga-regs"; reg = <0x4 0x0 0x40>; }; + + wdt@4,2000 { + compatible = "gef,fpga-wdt"; + reg = <0x4 0x2000 0x8>; + interrupts = <0x1a 0x4>; + interrupt-parent = <&gef_pic>; + }; + /* Second watchdog available, driver currently supports one. + wdt@4,2010 { + compatible = "gef,fpga-wdt"; + reg = <0x4 0x2010 0x8>; + interrupts = <0x1b 0x4>; + interrupt-parent = <&gef_pic>; + }; + */ gef_pic: pic@4,4000 { #interrupt-cells = <1>; interrupt-controller; |